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RISC-V_Verilog/sim/Makefile
brice.boisson 0e72c3a2e6 Add: Makefile
2023-10-11 17:43:36 +09:00

5 lines
70 B
Makefile

all:
vsim -c -do "do simu.do; quit -f"
debug:
vsim -do "do simu.do"