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0fa44c183028bb8b2efbd180475e689b2b711af6
RISC-V_Verilog/scripts
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brice.boisson 7949850418 Add: new test source code + Fix: gen_bin script and bin path
2023-11-25 23:18:24 +09:00
..
gen_simu_do.sh
Add: new make way enabling multiple asm generated test
2023-11-22 11:35:08 +09:00
gen_test.py
Add: new test source code + Fix: gen_bin script and bin path
2023-11-25 23:18:24 +09:00
get_bin.sh
Add: new test source code + Fix: gen_bin script and bin path
2023-11-25 23:18:24 +09:00
run_test.sh
Fix: clean environment between two test
2023-11-24 19:47:36 +09:00
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