112 lines
2.5 KiB
Verilog
112 lines
2.5 KiB
Verilog
module risc_v_cpu (input clock, reset, output [31:0] out);
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wire [31:0] instruction;
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wire [31:0] imm;
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wire reg_we;
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wire [1:0] reg_sel_data_in;
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wire [4:0] reg_sel_out_a, reg_sel_out_b, reg_sel_in;
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wire [31:0] reg_data_out_a, reg_data_out_b, reg_data_in;
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wire alu_src, alu_not;
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wire [3:0] alu_func;
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wire [31:0] alu_in_b, alu_out;
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wire mem_we;
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wire [31:0] mem_out;
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wire pc_is_jmp;
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wire [1:0] pc_is_branch, pc_sel_in;
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wire [31:0] pc_addr, pc_new_addr;
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decoder decoder (
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.instruction(instruction),
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.imm(imm),
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.reg_we(reg_we),
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.reg_sel_data_in(reg_sel_data_in),
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.reg_sel_out_a(reg_sel_out_a),
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.reg_sel_out_b(reg_sel_out_b),
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.reg_sel_in(reg_sel_in),
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.alu_src(alu_src),
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.alu_func(alu_func),
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.mem_we(mem_we),
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.pc_is_branch(pc_is_branch),
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.pc_is_jmp(pc_is_jmp),
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.alu_not(alu_not)
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);
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registers_bank registers_bank (
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.clock(clock),
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.reset(reset),
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.we(reg_we),
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.sel_in(reg_sel_in),
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.sel_out_a(reg_sel_out_a),
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.sel_out_b(reg_sel_out_b),
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.data_in(reg_data_in),
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.data_out_a(reg_data_out_a),
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.data_out_b(reg_data_out_b)
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);
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mux2_1 mux2_1_1 (
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.A(reg_data_out_b),
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.B(imm),
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.S(alu_src),
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.O(alu_in_b)
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);
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alu alu (
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.input_a(reg_data_out_a),
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.input_b(alu_in_b),
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.op_code(alu_func),
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.out(alu_out)
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);
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mux2_1 #(2) mux2_1_2 (
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.A(pc_is_branch),
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.B({alu_out[1], (alu_not ? ~alu_out[0] : alu_out[0])}),
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.S(pc_is_jmp),
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.O(pc_sel_in)
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);
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mux4_1 mux4_1_1 (
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.A(pc_addr + 4),
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.B(pc_addr + imm),
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.C(alu_out),
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.D(0),
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.S(pc_sel_in),
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.O(pc_new_addr)
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);
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program_counter program_counter (
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.clock(clock),
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.reset(reset),
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.pc_new_addr(pc_new_addr),
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.pc_addr(pc_addr)
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);
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instruction uut_instruction (
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.address(pc_addr),
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.instruction(instruction)
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);
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memory memory (
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.clock(clock),
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.reset(reset),
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.we(mem_we),
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.address(alu_out),
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.data_in(reg_data_out_b),
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.data_out(mem_out)
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);
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mux4_1 mux4_1_2 (
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.A(alu_out),
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.B(mem_out),
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.C(pc_addr + 4),
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.D(pc_addr + alu_out),
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.S(reg_sel_data_in),
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.O(reg_data_in)
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);
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endmodule
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