36 lines
937 B
Verilog
36 lines
937 B
Verilog
module module_program_counter (input clock, reset,
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input is_jmp, alu_not,
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input [1:0] is_branch,
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input [31:0] alu_out, imm,
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output [31:0] addr);
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wire [1:0] sel_in;
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wire [31:0] pc_addr, new_addr;
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mux2_1 #(2) mux2_pc_sel_branch (
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.in_1(is_branch),
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.in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}),
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.sel(is_jmp),
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.out(sel_in)
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);
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mux4_1 mux4_pc_sel_in (
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.in_1(pc_addr + 4),
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.in_2(pc_addr + imm),
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.in_3(alu_out),
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.in_4(0),
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.sel(sel_in),
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.out(new_addr)
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);
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program_counter program_counter (
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.clock(clock),
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.reset(reset),
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.new_addr(new_addr),
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.pc_addr(pc_addr)
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);
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assign addr = pc_addr;
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endmodule
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