31 lines
861 B
Verilog
31 lines
861 B
Verilog
module module_registers_bank (input clock, reset, we,
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input [1:0] sel_data_in,
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input [4:0] sel_in, sel_out_a, sel_out_b,
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input [31:0] alu_out, mem_out, pc_addr,
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output [31:0] data_out_a, data_out_b);
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wire [31:0] data_in;
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mux4_1 mux4_reg_sel_data_in (
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.in_1(alu_out),
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.in_2(mem_out),
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.in_3(pc_addr + 4),
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.in_4(pc_addr + alu_out),
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.sel(sel_data_in),
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.out(data_in)
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);
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registers_bank registers_bank (
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.clock(clock),
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.reset(reset),
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.we(we),
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.sel_in(sel_in),
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.sel_out_a(sel_out_a),
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.sel_out_b(sel_out_b),
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.data_in(data_in),
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.data_out_a(data_out_a),
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.data_out_b(data_out_b)
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);
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endmodule
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