96 lines
2.3 KiB
Verilog
96 lines
2.3 KiB
Verilog
module risc_v_cpu (input clock, reset,
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output [31:0] out);
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wire [31:0] instruction;
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wire [31:0] imm;
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wire reg_we;
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wire [1:0] reg_sel_data_in;
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wire [4:0] reg_sel_out_a, reg_sel_out_b, reg_sel_in;
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wire [31:0] reg_data_out_a, reg_data_out_b;
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wire alu_src, alu_not;
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wire [3:0] alu_func;
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wire [31:0] alu_out;
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wire mem_we;
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wire [1:0] mem_func_in;
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wire [2:0] mem_func_out;
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wire [31:0] mem_out;
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wire pc_is_jmp;
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wire [1:0] pc_is_branch;
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wire [31:0] pc_addr;
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decoder decoder (
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.instruction(instruction),
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.imm(imm),
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.reg_we(reg_we),
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.reg_sel_data_in(reg_sel_data_in),
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.reg_sel_out_a(reg_sel_out_a),
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.reg_sel_out_b(reg_sel_out_b),
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.reg_sel_in(reg_sel_in),
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.alu_src(alu_src),
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.alu_func(alu_func),
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.mem_we(mem_we),
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.mem_func_in(mem_func_in),
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.mem_func_out(mem_func_out),
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.pc_is_branch(pc_is_branch),
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.pc_is_jmp(pc_is_jmp),
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.alu_not(alu_not)
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);
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module_registers_bank module_registers_bank (
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.clock(clock),
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.reset(reset),
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.we(reg_we),
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.sel_data_in(reg_sel_data_in),
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.sel_in(reg_sel_in),
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.sel_out_a(reg_sel_out_a),
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.sel_out_b(reg_sel_out_b),
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.alu_out(alu_out),
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.mem_out(mem_out),
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.pc_addr(pc_addr),
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.data_out_a(reg_data_out_a),
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.data_out_b(reg_data_out_b)
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);
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module_alu module_alu (
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.src(alu_src),
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.func(alu_func),
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.reg_in_a(reg_data_out_a),
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.reg_in_b(reg_data_out_b),
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.imm(imm),
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.out(alu_out)
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);
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module_program_counter module_program_counter (
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.clock(clock),
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.reset(reset),
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.is_jmp(pc_is_jmp),
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.is_branch(pc_is_branch),
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.alu_not(alu_not),
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.alu_out(alu_out),
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.imm(imm),
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.addr(pc_addr)
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);
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instruction uut_instruction (
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.address(pc_addr),
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.instruction(instruction)
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);
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memory memory (
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.clock(clock),
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.reset(reset),
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.we(mem_we),
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.func_in(mem_func_in),
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.func_out(mem_func_out),
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.address(alu_out),
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.data_in(reg_data_out_b),
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.data_out(mem_out)
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);
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endmodule
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