42 lines
1.3 KiB
Verilog
42 lines
1.3 KiB
Verilog
module registers_bank (input clock, reset, we,
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input [4:0] select_d, select_a, select_b,
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input [31:0] input_d,
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output [31:0] output_a, output_b);
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reg [31:0] registers[31:0];
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assign registers[0] = 32'b0;
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assign registers[1] = 32'b0;
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assign registers[2] = 32'b0;
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assign registers[3] = 32'b0;
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assign registers[4] = 32'b0;
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assign registers[5] = 32'b0;
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assign registers[6] = 32'b0;
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assign registers[7] = 32'b0;
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assign registers[8] = 32'b0;
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assign registers[9] = 32'b0;
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assign registers[10] = 32'b0;
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assign registers[11] = 32'b0;
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assign registers[12] = 32'b0;
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assign registers[13] = 32'b0;
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assign registers[14] = 32'b0;
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assign registers[15] = 32'b0;
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assign registers[16] = 32'b0;
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assign registers[17] = 32'b0;
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assign registers[18] = 32'b0;
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assign registers[19] = 32'b0;
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assign registers[20] = 32'b0;
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assign registers[21] = 32'b0;
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always @(posedge clock, posedge reset) begin
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if (reset == 1)
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registers[0] <= 32'b0;
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else if (we == 1)
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registers[select_d] <= input_d;
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end
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assign output_a = registers[select_a];
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assign output_b = registers[select_b];
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endmodule
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