29 lines
791 B
Verilog
29 lines
791 B
Verilog
module alu (input [31:0] in_a, in_b,
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input [3:0] func,
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output reg [31:0] out);
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`include "alu_func.vh"
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reg signed [31:0] s_in_a;
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reg signed [31:0] s_in_b;
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always@ (*) begin
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s_in_a = in_a;
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s_in_b = in_b;
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case (func)
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ADD : out <= in_a + in_b;
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SUB : out <= in_a - in_b;
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SLL : out <= in_a << in_b;
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SLT : out <= (s_in_a < s_in_b) ? 1 : 0;
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SLTU : out <= (in_a < in_b) ? 1 : 0;
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XOR : out <= in_a ^ in_b;
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SRL : out <= in_a >> in_b;
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SRA : out <= s_in_a >>> in_b;
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OR : out <= in_a | in_b;
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AND : out <= in_a & in_b;
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default : out <= 32'b0;
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endcase
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end
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endmodule
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