RISC-V_Verilog/scripts
brice.boisson 9ac36fa030 Fix: clean environment between two test 2023-11-24 19:47:36 +09:00
..
gen_simu_do.sh Add: new make way enabling multiple asm generated test 2023-11-22 11:35:08 +09:00
gen_test.py Add: new make way enabling multiple asm generated test 2023-11-22 11:35:08 +09:00
get_bin.sh Add: new make way enabling multiple asm generated test 2023-11-22 11:35:08 +09:00
run_test.sh Fix: clean environment between two test 2023-11-24 19:47:36 +09:00