8 lines
196 B
Verilog
8 lines
196 B
Verilog
module mux2_1 #(parameter BUS_SIZE = 32)
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(input [BUS_SIZE - 1:0] A, B,
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input S,
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output [BUS_SIZE - 1:0] O);
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assign O = S ? B : A;
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endmodule |