21 lines
616 B
Verilog
21 lines
616 B
Verilog
module registers_bank (input clock, reset, we,
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input [4:0] sel_in, sel_out_a, sel_out_b,
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input [31:0] data_in,
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output [31:0] data_out_a, data_out_b);
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reg [31:0] registers[31:0];
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assign registers[0] = 32'b0;
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always @(posedge clock, posedge reset) begin
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if (reset == 1)
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registers[0] <= 32'b0;
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else if (we == 1 && sel_in != 5'b00000)
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registers[sel_in] <= data_in;
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end
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assign data_out_a = registers[sel_out_a];
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assign data_out_b = registers[sel_out_b];
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endmodule
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