42 lines
913 B
Verilog
42 lines
913 B
Verilog
`timescale 1ns / 1ps
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module tb_alu ();
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// Design Inputs and outputs
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reg [31:0] in_a;
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reg [31:0] in_b;
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reg [2:0] op_code;
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wire [31:0] out;
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// DUT instantiation
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alu alu (
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.input_a(in_a),
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.input_b(in_b),
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.op_code(op_code),
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.out(out)
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);
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// Test stimulus
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initial begin
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// Use the monitor task to display the FPGA IO
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$monitor("time=%3d, in_a=%d, in_b=%d, ctrl=%b, q=%d \n",
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$time, in_a, in_b, op_code, out);
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// Generate each input with a 20 ns delay between them
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in_a = 1'b0;
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in_b = 1'b0;
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op_code = 3'b000;
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#20
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if (out !== 0) $display("[FAILED] output should be 0");
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in_a = 1'b1;
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#20
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if (out !== 1) $display("[FAILED] output should be 1");
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in_b = 1'b1;
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#20
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if (out !== 2) $display("[FAILED] output should be 2");
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op_code = 3'b001;
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#20
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if (out !== 2) $display("[FAILED] output should be 2");
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end
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endmodule : tb_alu
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