RISC-V_Verilog/rtl
brice.boisson 5e93084239 Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench 2023-11-28 14:24:30 +09:00
..
alu.v Fix: change alu op_code to func 2023-10-24 19:39:42 +09:00
alu_func.vh Add: named parameter for ALU func | alu test case 2023-10-24 10:49:29 +09:00
decoder.v Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench 2023-11-28 14:24:30 +09:00
instruction.v Add: loop and multiplication source code test | expend instruction memory size | Fix: on empty test file 2023-11-27 14:27:09 +09:00
mem_func.vh Add: save reg in stack on entry of fun | Fix: set right mem_in func in decoder | set right mem_out code | test bench 2023-11-28 14:24:30 +09:00
memory.v Add: memory managing different size of opperand 2023-10-26 16:36:32 +09:00
mux2_1.v Fix: clean name [3] 2023-10-23 14:15:21 +09:00
mux4_1.v Fix: clean name [3] 2023-10-23 14:15:21 +09:00
op_code.vh Fix: use parameter to name op code 2023-10-23 10:10:49 +09:00
program_counter.v Fix: clean name [3] 2023-10-23 14:15:21 +09:00
registers_bank.v Fix: clean name [3] 2023-10-23 14:15:21 +09:00
risc-v_cpu_top.v Add: Archi 2023-10-10 16:13:26 +09:00
risc_v_cpu.v Add: test from gcc 2023-11-20 22:20:42 +09:00