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RISC-V_Verilog/Makefile
brice.boisson 0e72c3a2e6 Add: Makefile
2023-10-11 17:43:36 +09:00

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Makefile

all: simulation
$(MAKE) -C sim $@
debug: simulation
$(MAKE) -C sim $@
simulation:
./scripts/gen_simu_do.sh $(TARGET) $(WAVE)
clean:
rm -rf sim/work
rm -rf sim/transcript
rm -rf sim/vsim.wlf
rm -rf sim/simu.do