33 lines
1.0 KiB
Verilog
33 lines
1.0 KiB
Verilog
module instruction (input [31:0] address,
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output [31:0] instruction);
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reg [31:0] memory [63:0];
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// ADDi $1, R[0], R[6] - R[6] = 1
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// "000000000001_00000_000_00110_0010000"
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assign memory[0] = 32'b00000000000100000000001100010000;
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// ADDi $0, R[0], R[7] - R[7] = 0
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// "000000000000_00000_000_00111_0010000"
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assign memory[4] = 32'b00000000000000000000001110010000;
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// ADDi $0, R[6], R[8] - R[8] = R[6]
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// "000000000000_00110_000_01000_0010000"
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assign memory[8] = 32'b00000000000000110000010000010000;
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// ADD R[7], R[6], R[6] - R[6] = R[7] + R[6]
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// "0000000_00111_00110_000_00110_0110000"
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assign memory[12] = 32'b00000000011100110000001100110000;
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// ADDi $0, R[8], R[7] - R[7] = R[8]
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// "000000000000_01000_000_00111_0010000"
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assign memory[16] = 32'b00000000000001000000001110010000;
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// JUMP
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// 11111111111111111101_00111_1101100
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assign memory[20] = 32'b11111111111111110100001011101100;
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assign instruction = memory[address];
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endmodule
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