250 lines
9.1 KiB
Verilog
250 lines
9.1 KiB
Verilog
module decoder (input [31:0] instruction,
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output reg [31:0] immediate,
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output reg we_reg, adder_pc, data_out,
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output reg [1:0] input_reg,
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output reg [4:0] select_a, select_b, select_d,
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output reg source_alu,
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output reg [3:0] op_code_alu,
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output reg mem_we,
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output reg [1:0] jmp_pc,
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output reg b_pc, alu_not);
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function [3:0] get_op_code_alu(input [2:0] op_code, input arithmetic);
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begin
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case (op_code)
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3'b000 : get_op_code_alu = arithmetic ? 4'b0001 : 4'b0000;
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3'b001 : get_op_code_alu = 4'b0010;
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3'b010 : get_op_code_alu = 4'b0011;
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3'b011 : get_op_code_alu = 4'b0011;
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3'b100 : get_op_code_alu = 4'b0100;
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3'b101 : get_op_code_alu = arithmetic ? 4'b0111 : 4'b0101;
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3'b110 : get_op_code_alu = 4'b1000;
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3'b111 : get_op_code_alu = 4'b1010;
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3'b111 : get_op_code_alu = 4'b1011;
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default : get_op_code_alu= 4'b0000;
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endcase
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end
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endfunction
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function [3:0] get_op_code_alu_imm(input [2:0] op_code, input arithmetic);
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begin
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case (op_code)
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3'b000 : get_op_code_alu_imm = 4'b0000;
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3'b001 : get_op_code_alu_imm = 4'b0010;
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3'b010 : get_op_code_alu_imm = 4'b0011;
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3'b011 : get_op_code_alu_imm = 4'b0100;
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3'b100 : get_op_code_alu_imm = 4'b0101;
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3'b101 : get_op_code_alu_imm = arithmetic ? 4'b1000 : 4'b0111;
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3'b110 : get_op_code_alu_imm = 4'b1001;
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3'b111 : get_op_code_alu_imm = 4'b1010;
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3'b111 : get_op_code_alu_imm = 4'b1011;
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default : get_op_code_alu_imm = 4'b0000;
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endcase
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end
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endfunction
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function [3:0] branch_op_code(input [2:0] op_code);
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begin
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case (op_code)
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3'b000 : branch_op_code = 4'b0001;
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3'b001 : branch_op_code = 4'b0001;
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3'b010 : branch_op_code = 4'b0011;
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3'b011 : branch_op_code = 4'b0011;
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3'b100 : branch_op_code = 4'b0011;
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3'b101 : branch_op_code = 4'b0011;
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default : branch_op_code = 4'b0000;
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endcase
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end
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endfunction
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function branch_not(input [2:0] op_code);
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begin
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case (op_code)
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3'b000 : branch_not = 1;
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3'b001 : branch_not = 0;
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3'b010 : branch_not = 0;
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3'b011 : branch_not = 1;
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3'b100 : branch_not = 0;
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3'b101 : branch_not = 1;
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default : branch_not = 0;
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endcase
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end
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endfunction
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// TODO - Manage ALU OP CODE and IMM Extension
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always @(*) begin
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case (instruction[6:2])
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5'b01100 : begin // OP - Add, ...
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immediate = 0;
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we_reg = 1;
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adder_pc = 0;
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data_out = 0;
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input_reg = 2'b01;
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select_a = instruction[19:15];
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select_b = instruction[24:20];
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select_d = instruction[11:7];
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source_alu = 0;
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op_code_alu = get_op_code_alu(instruction[14:12], instruction[30]);
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mem_we = 0;
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jmp_pc = 2'b00;
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b_pc = 0;
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alu_not = 0;
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alu_not = 0;
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end
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5'b00100 : begin // OP-IMM - Addi, ...
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immediate[11:0] = instruction[31:20];
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immediate[31:12] = (instruction[14:12] == 3'b011 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
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we_reg = 1;
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adder_pc = 0;
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data_out = 0;
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input_reg = 2'b01;
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select_a = instruction[19:15];
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select_b = 5'b00000;
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select_d = instruction[11:7];
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source_alu = 1;
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op_code_alu = get_op_code_alu_imm(instruction[14:12], instruction[30]);
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mem_we = 0;
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jmp_pc = 2'b00;
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b_pc = 0;
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alu_not = 0;
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end
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5'b00000 : begin // LOAD - Lw, ...
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immediate[11:0] = instruction[31:20];
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immediate[31:12] = (instruction[14:12] == 3'b100 || instruction[14:12] == 3'b101 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
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we_reg = 1;
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adder_pc = 0;
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data_out = 0;
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input_reg = 2'b10;
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select_a = instruction[19:15];
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select_b = 5'b00000;
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select_d = instruction[11:7];
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source_alu = 1;
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op_code_alu = 3'b000;
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mem_we = 0;
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jmp_pc = 2'b00;
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b_pc = 0;
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alu_not = 0;
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end
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5'b01000 : begin // STORE - Sw, ...
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immediate[11:0] = {instruction[31:25], instruction[11:7]};
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immediate[31:12] = (instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
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we_reg = 0;
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adder_pc = 0;
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data_out = 0;
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input_reg = 2'b01;
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select_a = instruction[19:15];
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select_b = instruction[24:20];
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select_d = 5'b00000;
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source_alu = 1;
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op_code_alu = 3'b000;
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mem_we = 1;
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jmp_pc = 2'b00;
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b_pc = 0;
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alu_not = 0;
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end
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5'b11000 : begin // BRANCH - Beq, ...
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immediate[11:0] = {instruction[31:25], instruction[11:7]};
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immediate[31:12] = (instruction[14:12] == 3'b110 || instruction[14:12] == 3'b111 || instruction[31] == 0) ? 12'b00000000000000000000 : 12'b11111111111111111111;
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we_reg = 0;
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adder_pc = 0;
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data_out = 0;
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input_reg = 2'b01;
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select_a = instruction[19:15];
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select_b = instruction[24:20];
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select_d = 5'b00000;
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source_alu = 0;
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op_code_alu = branch_op_code(instruction[14:12]);
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mem_we = 0;
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jmp_pc = 2'b00;
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b_pc = 1;
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alu_not = branch_not(instruction[14:12]);
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end
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5'b11011 : begin // JUMP - Jal
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immediate[19:0] = instruction[31:12];
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immediate[31:20] = (instruction[31] == 0) ? 12'b000000000000 : 12'b111111111111;
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we_reg = 1;
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adder_pc = 0;
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data_out = 0;
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input_reg = 2'b00;
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select_a = 5'b00000;
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select_b = 5'b00000;
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select_d = instruction[11:7];
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source_alu = 0;
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op_code_alu = 3'b000;
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mem_we = 0;
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jmp_pc = 2'b01;
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b_pc = 0;
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alu_not = 0;
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end
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5'b11001 : begin // JUMP REG - Jalr
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immediate[19:0] = instruction[31:12];
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immediate[31:20] = (instruction[31] == 0) ? 12'b000000000000 : 12'b111111111111;
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we_reg = 1;
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adder_pc = 0;
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data_out = 0;
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input_reg = 2'b00;
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select_a = instruction[19:15];
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select_b = 5'b00000;
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select_d = instruction[11:7];
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source_alu = 0;
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op_code_alu = 3'b000;
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mem_we = 0;
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jmp_pc = 2'b10;
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b_pc = 0;
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alu_not = 0;
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end
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5'b01101 : begin // LUI - lui
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immediate = {instruction[31:12] << 12, 12'b000000000000};
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we_reg = 1;
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adder_pc = 0;
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data_out = 1;
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input_reg = 2'b01;
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select_a = 5'b00000;
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select_b = 5'b00000;
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select_d = instruction[11:7];
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source_alu = 1;
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op_code_alu = 3'b000;
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mem_we = 0;
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jmp_pc = 2'b00;
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b_pc = 0;
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alu_not = 0;
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end
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5'b00101 : begin // AUIPC - auipc
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immediate = {instruction[31:12] << 12, 12'b000000000000};
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we_reg = 1;
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adder_pc = 1;
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data_out = 1;
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input_reg = 2'b00;
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select_a = 5'b00000;
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select_b = 5'b00000;
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select_d = instruction[11:7];
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source_alu = 0;
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op_code_alu = 3'b000;
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mem_we = 0;
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jmp_pc = 2'b00;
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b_pc = 0;
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alu_not = 0;
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end
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default : begin // NOP
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immediate = 32'b0;
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we_reg = 0;
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adder_pc = 0;
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data_out = 0;
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input_reg = 2'b00;
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select_a = 5'b00000;
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select_b = 5'b00000;
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select_d = 5'b00000;
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source_alu = 0;
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op_code_alu = 3'b000;
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mem_we = 0;
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jmp_pc = 2'b00;
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b_pc = 0;
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alu_not = 0;
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end
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endcase
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end
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endmodule
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