RISC-V_Verilog/scripts
brice.boisson 7d60960831 Add: generate test from comment in assembly file 2023-11-21 18:36:10 +09:00
..
gen_simu_do.sh Add: script 2023-11-20 14:21:26 +09:00
gen_test.py Add: generate test from comment in assembly file 2023-11-21 18:36:10 +09:00
get_bin.sh Add: test from gcc 2023-11-20 22:20:42 +09:00