brice.boisson 89a66cd244 Add: set every part of the pipeline in a module (decode, registers, alu, pc, instr_mem, mem)

2023-10-27 12:46:13 +09:00

..

tb_alu.v

Fix: change alu op_code to func

2023-10-24 19:39:42 +09:00

tb_mux2_1.v

Add: tb macro to assert

2023-10-23 17:34:37 +09:00

tb_mux4_1.v

Add: tb registers bank

2023-10-24 20:08:36 +09:00

tb_registers_bank.v

Add: set every part of the pipeline in a module (decode, registers, alu, pc, instr_mem, mem)

2023-10-27 12:46:13 +09:00

tb_risc_v_cpu.v

Add: set every part of the pipeline in a module (decode, registers, alu, pc, instr_mem, mem)

2023-10-27 12:46:13 +09:00

tb_tools.vh

Add: tb_risc_v fibonacci compute

2023-10-24 21:19:24 +09:00