75 lines
2.3 KiB
Verilog
75 lines
2.3 KiB
Verilog
`timescale 1ns / 1ps
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`include "tb_tools.vh"
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module tb_registers_bank ();
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reg clk;
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reg reset;
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reg we;
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reg [4:0] sel_in;
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reg [4:0] sel_out_a;
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reg [4:0] sel_out_b;
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reg [31:0] data_in;
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wire [31:0] data_out_a;
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wire [31:0] data_out_b;
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registers_bank registers_bank (
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.clock(clk),
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.reset(reset),
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.we(we),
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.sel_in(sel_in),
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.sel_out_a(sel_out_a),
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.sel_out_b(sel_out_b),
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.data_in(data_in),
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.data_out_a(data_out_a),
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.data_out_b(data_out_b)
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);
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initial begin
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reset = 1'b1;
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#10
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reset = 1'b0;
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end
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initial begin
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clk = 1'b0;
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for (i = 0; i < 100; i = i + 1) begin
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#1 clk = ~clk;
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end
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end
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initial begin
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we = 1'b0;
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sel_in = 5'b00000;
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sel_out_a = 5'b00000;
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sel_out_b = 5'b00000;
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data_in = 32'b0;
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`assert("registers_bank we: 0, sel_in: 0, sel_out_a: 0, sel_out_b: 0, data_in: 0", data_out_a, 0)
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we = 1'b1;
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data_in = 32'b1;
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`assert("registers_bank we: 1, sel_in: 0, sel_out_a: 0, sel_out_b: 0, data_in: 1", data_out_a, 0)
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sel_in = 5'b00001;
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`assert("registers_bank we: 1, sel_in: 1, sel_out_a: 0, sel_out_b: 0, data_in: 1", data_out_a, 0)
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sel_out_a = 5'b00001;
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`assert("registers_bank we: 1, sel_in: 1, sel_out_a: 1, sel_out_b: 0, data_in: 1", data_out_a, 1)
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`assert("registers_bank we: 1, sel_in: 1, sel_out_a: 1, sel_out_b: 0, data_in: 1", data_out_b, 0)
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sel_out_b = 5'b00001;
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`assert("registers_bank we: 1, sel_in: 1, sel_out_a: 1, sel_out_b: 1, data_in: 1", data_out_b, 1)
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we = 1'b0;
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data_in = 32'b11;
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`assert("registers_bank we: 0, sel_in: 1, sel_out_a: 1, sel_out_b: 1, data_in: 3", data_out_a, 1)
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`assert("registers_bank we: 0, sel_in: 1, sel_out_a: 1, sel_out_b: 1, data_in: 3", data_out_b, 1)
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data_in = 32'b111;
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sel_in = 5'b11111;
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sel_out_a = 5'b11111;
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we = 1'b1;
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`assert("registers_bank we: 1, sel_in: 31, sel_out_a: 31, sel_out_b: 1, data_in: 7", data_out_a, 7)
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`assert("registers_bank we: 1, sel_in: 31, sel_out_a: 31, sel_out_b: 1, data_in: 7", data_out_b, 1)
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`end_message
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end
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endmodule : tb_registers_bank
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