47 lines
1.8 KiB
Verilog
47 lines
1.8 KiB
Verilog
module memory (input clock, reset,
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input we,
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input [1:0] func_in,
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input [2:0] func_out,
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input [31:0] address,
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input [31:0] data_in,
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output reg [31:0] data_out);
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`include "mem_func.vh"
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reg [7:0] memory [127:0];
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always @(posedge clock, posedge reset) begin
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if (reset == 1)
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memory[0] <= 8'b0;
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else if (we == 1) begin
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case (func_in)
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SB : begin
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memory[address] <= data_in[7:0];
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end
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SH : begin
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memory[address] <= data_in[7:0];
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memory[address + 1] <= data_in[15:8];
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end
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SW : begin
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memory[address] <= data_in[7:0];
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memory[address + 1] <= data_in[15:8];
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memory[address + 2] <= data_in[23:16];
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memory[address + 3] <= data_in[31:24];
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end
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endcase
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end
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end
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always @(*) begin
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case (func_out)
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LB : data_out <= {(memory[address][7] == 1'b1 ? 24'b111111111111111111111111 : 24'b000000000000000000000000), memory[address]};
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LH : data_out <= {(memory[address][15] == 1'b1 ? 16'b1111111111111111 : 16'b0000000000000000), memory[address], memory[address]};
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LW : data_out <= {memory[address + 3], memory[address + 2], memory[address + 1], memory[address]};
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LBU : data_out <= {24'b000000000000000000000000, memory[address]};
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LHU : data_out <= {16'b0000000000000000, memory[address]};
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default : data_out <= 32'b00000000000000000000000000000000;
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endcase
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end
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endmodule
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