8 lines
235 B
Verilog
8 lines
235 B
Verilog
module mux2_1 #(parameter BUS_SIZE = 32)
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(input [BUS_SIZE - 1:0] in_1, in_2,
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input sel,
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output [BUS_SIZE - 1:0] out);
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assign out = sel ? in_2 : in_1;
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endmodule |