RISC-V_Verilog/scripts
brice.boisson 9d82414a58 Fix: remove print in gen_test.py 2023-11-26 22:08:00 +09:00
..
gen_simu_do.sh Add: new make way enabling multiple asm generated test 2023-11-22 11:35:08 +09:00
gen_test.py Fix: remove print in gen_test.py 2023-11-26 22:08:00 +09:00
get_bin.sh Add: new test source code + Fix: gen_bin script and bin path 2023-11-25 23:18:24 +09:00
run_test.sh Fix: clean environment between two test 2023-11-24 19:47:36 +09:00