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RISC-V_Verilog
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a0a1b26b83
RISC-V_Verilog
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brice.boisson
e0b2ada62f
Add: error message when the number of ran test is lower than the number of test present is the assmbly file (the number of ran test can be superior, and in few time lower that's why it's only a warning
2023-11-30 14:43:01 +09:00
..
gen_simu_do.sh
Add: new make way enabling multiple asm generated test
2023-11-22 11:35:08 +09:00
gen_test.py
Add: error message when the number of ran test is lower than the number of test present is the assmbly file (the number of ran test can be superior, and in few time lower that's why it's only a warning
2023-11-30 14:43:01 +09:00
get_bin.sh
Add: new test source code + Fix: gen_bin script and bin path
2023-11-25 23:18:24 +09:00
run_test.sh
Add: error message when the number of ran test is lower than the number of test present is the assmbly file (the number of ran test can be superior, and in few time lower that's why it's only a warning
2023-11-30 14:43:01 +09:00