brice
/
RISC-V_Verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
RISC-V_Verilog/sim/Makefile

6 lines
91 B
Makefile
Raw Blame History

all:
./../scripts/run_test.sh $(TARGET)
debug:
./../scripts/run_test.sh $(TARGET) debug
Reference in New Issue View Git Blame Copy Permalink