RISC-V_Verilog/rtl
brice.boisson 67c71565c0 Fix: memory addressing 32 to 8 bits 2023-10-24 21:52:07 +09:00
..
alu.v Fix: change alu op_code to func 2023-10-24 19:39:42 +09:00
alu_func.vh Add: named parameter for ALU func | alu test case 2023-10-24 10:49:29 +09:00
decoder.v Fix: change alu op_code to func 2023-10-24 19:39:42 +09:00
instruction.v Fix: memory addressing 32 to 8 bits 2023-10-24 21:52:07 +09:00
memory.v Fix: memory addressing 32 to 8 bits 2023-10-24 21:52:07 +09:00
mux2_1.v Fix: clean name [3] 2023-10-23 14:15:21 +09:00
mux4_1.v Fix: clean name [3] 2023-10-23 14:15:21 +09:00
op_code.vh Fix: use parameter to name op code 2023-10-23 10:10:49 +09:00
program_counter.v Fix: clean name [3] 2023-10-23 14:15:21 +09:00
registers_bank.v Fix: clean name [3] 2023-10-23 14:15:21 +09:00
risc-v_cpu_top.v Add: Archi 2023-10-10 16:13:26 +09:00
risc_v_cpu.v Fix: change alu op_code to func 2023-10-24 19:39:42 +09:00