20 lines
623 B
Verilog
20 lines
623 B
Verilog
module alu (input [31:0] input_a, input_b,
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input [2:0] op_code,
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output reg [31:0] out);
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always@ (*) begin
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case (op_code)
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3'b000 : out <= input_a + input_b;
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3'b001 : out <= input_a << input_b;
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3'b010 : out <= (input_a < input_b) ? 1 : 0;
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3'b011 : out <= input_a ^ input_b;
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3'b100 : out <= input_a >> input_b;
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3'b101 : out <= input_a >>> input_b;
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3'b110 : out <= input_a | input_b;
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3'b111 : out <= input_a & input_b;
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default : out <= 32'b0;
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endcase
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end
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endmodule
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