19 lines
456 B
Verilog
19 lines
456 B
Verilog
module instruction (input clock, reset,
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input we,
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input [31:0] address,
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input [31:0] data_in
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output [31:0] data_out);
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reg [63:0] memory [31:0];
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always @(posedge clock, reset) begin
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if (reset == 1)
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memory[0] <= 32'b0;
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else if (we == 1)
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memory[address] <= data_in;
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end
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assign data_out = memory[address];
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endmodule
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