75 lines
2.1 KiB
Verilog
75 lines
2.1 KiB
Verilog
`timescale 1ns / 1ps
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`include "tb_tools.vh"
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module tb_risc_v_cpu ();
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reg clk;
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reg reset;
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integer i;
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wire [31:0] out;
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/* File management variable */
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integer bin_file_inputs;
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reg [8:0] read_instruction_1;
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reg [8:0] read_instruction_2;
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reg [8:0] read_instruction_3;
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reg [8:0] read_instruction_4;
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risc_v_cpu risc_v_cpu (
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.clock(clk),
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.reset(reset),
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.out(out)
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);
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initial begin
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/* Reset */
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reset = 1'b1;
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#10
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reset = 1'b0;
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clk = 1'b0;
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/* Loading Test From File */
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/* Loading Binary File */
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bin_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.bin", "r");
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if (bin_file_inputs == 0) begin
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$display("data_file handle was NULL");
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$finish;
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end
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i = 0;
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while (!$feof(bin_file_inputs))
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begin
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read_instruction_1 = $fgetc(bin_file_inputs);
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read_instruction_2 = $fgetc(bin_file_inputs);
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read_instruction_3 = $fgetc(bin_file_inputs);
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read_instruction_4 = $fgetc(bin_file_inputs);
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$display("read_instruction_1: %b", read_instruction_1);
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if (
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read_instruction_1[8] != 1'b1 &&
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read_instruction_2[8] != 1'b1 &&
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read_instruction_3[8] != 1'b1 &&
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read_instruction_4[8] != 1'b1
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) begin
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risc_v_cpu.uut_instruction.memory[i] = read_instruction_1[7:0];
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risc_v_cpu.uut_instruction.memory[i+1] = read_instruction_2[7:0];
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risc_v_cpu.uut_instruction.memory[i+2] = read_instruction_3[7:0];
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risc_v_cpu.uut_instruction.memory[i+3] = read_instruction_4[7:0];
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i = i + 4;
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end
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end
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for (i = 0; i < 100; i = i + 1) begin
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`next_cycle
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// run
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end
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// final test
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`assert_no_wait("FOR LOOP - REG[5]: 1", risc_v_cpu.registers_bank.registers[5], 32'b1010)
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`end_message
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end
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endmodule : tb_risc_v_cpu
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