128 lines
4.2 KiB
Verilog
128 lines
4.2 KiB
Verilog
`timescale 1ns / 1ps
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`include "tb_tools.vh"
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module tb_alu ();
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`include "../rtl/alu_func.vh"
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reg [31:0] in_a;
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reg [31:0] in_b;
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reg [3:0] op_code;
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wire [31:0] out;
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alu alu (
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.in_a(in_a),
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.in_b(in_b),
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.op_code(op_code),
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.out(out)
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);
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initial begin
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// ALU - Add
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in_a = 32'b0;
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in_b = 32'b0;
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op_code = ADD;
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`assert("alu : 0 + 0", out, 0)
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in_a = 32'b1;
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`assert("alu : 1 + 0", out, 1)
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in_b = 32'b1;
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`assert("alu : 1 + 1", out, 2)
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op_code = 4'b0001;
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`assert("alu : 1 - 1", out, 0)
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// ALU - left shift
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in_a = 32'b1;
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in_b = 32'b1;
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op_code = SLL;
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`assert("alu : 1 << 1", out, 2)
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in_b = 32'b10;
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`assert("alu : 1 << 2", out, 4)
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in_a = 32'b11;
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`assert("alu : 3 << 2", out, 12)
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in_b = 32'b11110;
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`assert("alu : 3 << 30", out, 32'b11000000000000000000000000000000)
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in_b = 32'b11111;
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`assert("alu : 3 << 31", out, 32'b10000000000000000000000000000000)
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in_b = 32'b100000;
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`assert("alu : 3 << 31", out, 32'b00000000000000000000000000000000)
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// ALU - less than
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in_a = 32'b0;
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in_b = 32'b0;
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op_code = SLT;
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`assert("alu : 0 < 0", out, 0)
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in_b = 32'b10;
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`assert("alu : 0 << 2", out, 1)
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in_a = 32'b11;
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`assert("alu : 3 < 2", out, 0)
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in_b = 32'b11111111111111111111111111111111;
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in_a = 32'b11111111111111111111111111111111;
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`assert("alu : -1 < -1", out, 0)
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in_b = 32'b0;
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`assert("alu : -1 < 0", out, 1)
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in_a = 32'b10000000000000000000000000000000;
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in_b = 32'b10000000000000000000000000000001;
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`assert("alu : MIN_INT << MIN_INT + 1", out, 1)
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// ALU - xor
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in_a = 32'b0;
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in_b = 32'b0;
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op_code = XOR;
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`assert("alu : 0 ^ 0", out, 32'b00000000000000000000000000000000)
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in_a = 32'b1;
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`assert("alu : 1 ^ 0", out, 32'b00000000000000000000000000000001)
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in_a = 32'b0;
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in_b = 32'b1;
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`assert("alu : 0 ^ 1", out, 32'b00000000000000000000000000000001)
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in_a = 32'b11111111111111111111111111111111;
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in_b = 32'b11111111111111111111111111111111;
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`assert("alu : MAX_INT ^ MAX_INT", out, 32'b00000000000000000000000000000000)
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in_a = 32'b00000000000000000000000000000000;
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in_b = 32'b11111111111111111111111111111111;
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`assert("alu : 0 ^ MAX_INT", out, 32'b11111111111111111111111111111111)
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in_a = 32'b00000011001000010001000011000000;
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in_b = 32'b10101111001011101110111111111011;
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`assert("alu : 00000011001000010001000011000000 ^ 10101111001011101110111111111011", out, 32'b10101100000011111111111100111011)
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// ALU - right shift
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in_a = 32'b1;
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in_b = 32'b1;
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op_code = SRL;
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`assert("alu : 1 >> 1", out, 0)
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in_a = 32'b10;
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`assert("alu : 2 >> 1", out, 1)
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in_a = 32'b11;
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`assert("alu : 3 >> 2", out, 1)
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in_a = 32'b11110;
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in_b = 32'b1;
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`assert("alu : 30 >> 1", out, 32'b1111)
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in_a = 32'b10000000000000000000000000000000;
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in_b = 32'b11111;
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`assert("alu : 1000...000 >> 31", out, 32'b00000000000000000000000000000001)
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in_a = 32'b10000000111100000000000111111111;
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in_b = 32'b11111;
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`assert("alu : 1000..111 >> 31", out, 32'b00000000000000000000000000000001)
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// // ALU - logical right shift
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// in_a = 32'b1;
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// in_b = 32'b1;
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// op_code = 4'b0110;
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// `assert("alu : 1 >> 1", out, 0)
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// in_a = 32'b10;
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// `assert("alu : 2 >> 1", out, 1)
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// in_a = 32'b11;
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// `assert("alu : 3 >> 2", out, 1)
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// in_a = 32'b11110;
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// in_b = 32'b1;
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// `assert("alu : 30 >> 1", out, 32'b1111)
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// in_a = 32'b10000000000000000000000000000000;
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// in_b = 32'b11111;
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// `assert("alu : 1000...000 >> 31", out, 32'b00000000000000000000000000000001)
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// in_a = 32'b10000000111100000000000111111111;
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// in_b = 32'b11111;
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// `assert("alu : 1000..111 >> 31", out, 32'b00000000000000000000000000000001)
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`end_message
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end
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endmodule : tb_alu
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