22 lines
683 B
Verilog
22 lines
683 B
Verilog
module memory (input clock, reset,
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input we,
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input [31:0] address,
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input [31:0] data_in,
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output [31:0] data_out);
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reg [7:0] memory [127:0];
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always @(posedge clock, posedge reset) begin
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if (reset == 1)
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memory[0] <= 8'b0;
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else if (we == 1)
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memory[address] <= data_in[7:0];
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memory[address + 1] <= data_in[15:8];
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memory[address + 2] <= data_in[23:16];
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memory[address + 3] <= data_in[31:24];
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end
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assign data_out = {memory[address + 3], memory[address + 2], memory[address + 1], memory[address]};
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endmodule
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