10 lines
258 B
Verilog
10 lines
258 B
Verilog
module mux4_1 #(parameter BUS_SIZE = 32)
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(input [BUS_SIZE - 1:0] A, B, C, D,
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input [1:0] S,
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output [BUS_SIZE - 1:0] O);
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assign O = S[1] ? (S[0] ? D : C)
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: (S[0] ? B : A);
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endmodule
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