Files
RISC-V_Verilog/tb/test_source_code/tb_riscv_cpu/test.S
brice.boisson 1f9a8ceebf Add: first test
2023-11-20 22:30:19 +09:00

9 lines
140 B
ArmAsm

# t0 = 0
li t0, 0
li t2, 10
loop_head:
bge t0, t2, loop_end
# Repeated code goes here
addi t0, t0, 1
j loop_head
loop_end: