174 lines
7.0 KiB
Verilog
174 lines
7.0 KiB
Verilog
`timescale 1ns / 1ps
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`include "tb_tools.vh"
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module tb_risc_v_cpu ();
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reg clk;
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reg reset;
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integer i;
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wire [31:0] out;
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/* File management variable */
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integer bin_file_inputs;
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integer code_file_inputs;
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reg [8:0] read_instruction_1;
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reg [8:0] read_instruction_2;
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reg [8:0] read_instruction_3;
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reg [8:0] read_instruction_4;
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reg [113:0] test [0:100];
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integer instruction_addr;
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reg [5:0] reg_number;
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reg [31:0] reg_test_value;
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integer curent_addr;
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integer res;
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reg [8:0] dump;
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risc_v_cpu risc_v_cpu (
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.clock(clk),
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.reset(reset),
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.out(out)
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);
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initial begin
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/* Reset */
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reset = 1'b1;
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#10
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reset = 1'b0;
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clk = 1'b0;
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/* Loading Test From File */
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/* Loading Binary File */
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bin_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.bin", "r");
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if (bin_file_inputs == 0) begin
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$display("bin file handle was NULL");
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$finish;
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end
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i = 0;
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while (!$feof(bin_file_inputs))
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begin
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read_instruction_1 = $fgetc(bin_file_inputs);
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read_instruction_2 = $fgetc(bin_file_inputs);
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read_instruction_3 = $fgetc(bin_file_inputs);
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read_instruction_4 = $fgetc(bin_file_inputs);
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if (
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read_instruction_1[8] != 1'b1 &&
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read_instruction_2[8] != 1'b1 &&
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read_instruction_3[8] != 1'b1 &&
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read_instruction_4[8] != 1'b1
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) begin
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risc_v_cpu.uut_instruction.memory[i] = read_instruction_1[7:0];
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risc_v_cpu.uut_instruction.memory[i+1] = read_instruction_2[7:0];
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risc_v_cpu.uut_instruction.memory[i+2] = read_instruction_3[7:0];
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risc_v_cpu.uut_instruction.memory[i+3] = read_instruction_4[7:0];
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i = i + 4;
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end
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end
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$fclose(bin_file_inputs);
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/* Extract Value to Test From File */
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code_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.tmp", "r");
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if (code_file_inputs == 0) begin
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$display("source code file handle was NULL");
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$finish;
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end
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i = 0;
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for (i = 0; i < 100; i = i + 1) begin // Fill test data structure of 1,
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test[i] = {114{1'b1}}; // to represent the empty state
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end
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while (!$feof(code_file_inputs))
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begin
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res = $fscanf(code_file_inputs, "%d:%d=%d\n", instruction_addr, reg_number, reg_test_value);
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if (res != 3) begin // If fscanf failed, the test file structure is wrong, then exit
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$display("Parsing test file failed");
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$finish;
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end
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if (test[instruction_addr][5:0] == 6'b111111) begin
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test[instruction_addr][5:0] = reg_number;
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test[instruction_addr][37:6] = reg_test_value;
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end else if (test[instruction_addr][43:38] == 6'b111111) begin
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$display ("1");
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test[instruction_addr][43:38] = reg_number;
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test[instruction_addr][75:44] = reg_test_value;
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end else if (test[instruction_addr][81:76] == 6'b111111) begin
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test[instruction_addr][81:76] = reg_number;
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test[instruction_addr][113:83] = reg_test_value;
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end
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end
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$fclose(code_file_inputs);
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/* Run The Program */
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for (i = 0; i < 100; i = i + 1) begin
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if (test[risc_v_cpu.program_counter.pc_addr][5:0] != 6'b111111) begin
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curent_addr = risc_v_cpu.program_counter.pc_addr;
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`next_cycle
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if (test[curent_addr][5:0] != 6'b111111) begin
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if (test[curent_addr][5:0] < 6'b100000) begin
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`assert_no_wait("TEST - REG", risc_v_cpu.registers_bank.registers[test[curent_addr][4:0]], test[curent_addr][37:6])
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end else if (test[curent_addr][5:0] == 6'b100000) begin
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`assert_no_wait("TEST - PC", risc_v_cpu.program_counter.pc_addr, test[curent_addr][37:6])
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end else if (test[curent_addr][5:0] > 6'b100000) begin
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`assert_no_wait("TEST - MEM", risc_v_cpu.memory.memory[test[curent_addr][5:0]], test[curent_addr][37:6])
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end
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end
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if (test[curent_addr][43:38] != 6'b111111) begin
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if (test[curent_addr][43:38] < 6'b100000) begin
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`assert_no_wait("TEST - REG", risc_v_cpu.registers_bank.registers[test[curent_addr][42:38]], test[curent_addr][75:44])
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end else if (test[curent_addr][43:38] == 6'b100000) begin
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`assert_no_wait("TEST - PC", risc_v_cpu.program_counter.pc_addr, test[curent_addr][75:44])
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end else if (test[curent_addr][43:38] > 6'b100000) begin
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`assert_no_wait("TEST - MEM", risc_v_cpu.memory.memory[test[curent_addr][43:38]], test[curent_addr][75:44])
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end
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end
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if (test[curent_addr][81:76] != 6'b111111) begin
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if (test[curent_addr][81:76] < 6'b100000) begin
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`assert_no_wait("TEST - REG", risc_v_cpu.registers_bank.registers[test[curent_addr][80:76]], test[curent_addr][81:76])
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end else if (test[curent_addr][81:76] == 6'b100000) begin
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`assert_no_wait("TEST - PC", risc_v_cpu.program_counter.pc_addr, test[curent_addr][113:83])
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end else if (test[curent_addr][81:76] > 6'b100000) begin
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`assert_no_wait("TEST - MEM", risc_v_cpu.memory.memory[test[curent_addr][81:76]], test[curent_addr][81:76])
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end
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end
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end
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else
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`next_cycle
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end
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/* Test State After Execution */
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code_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.final.tmp", "r");
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if (code_file_inputs == 0) begin
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$display("source code file handle was NULL");
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$finish;
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end
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while (!$feof(code_file_inputs))
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begin
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res = $fscanf(code_file_inputs, "%d=%d\n", reg_number, reg_test_value);
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if (res != 2) begin // If fscanf failed, the test file structure is wrong, then exit
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$display("Parsing test file failed");
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$finish;
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end
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if (reg_number < 6'b100000) begin
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`assert_no_wait("FINAL TEST - REG", risc_v_cpu.registers_bank.registers[reg_number[4:0]], reg_test_value)
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end else if (reg_number == 6'b100000) begin
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`assert_no_wait("FINAL TEST- PC", risc_v_cpu.program_counter.pc_addr, reg_test_value)
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end else if (reg_number > 6'b100000) begin
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`assert_no_wait("FINAL TEST - MEM", risc_v_cpu.memory.memory[test[curent_addr][5:0]], reg_test_value)
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end
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end
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`end_message
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end
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endmodule : tb_risc_v_cpu
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