128 lines
2.5 KiB
Verilog
128 lines
2.5 KiB
Verilog
module risc_v_cpu (input clock, reset, output [31:0] out);
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wire [31:0] in_b;
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wire [31:0] alu_out;
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wire [31:0] instruction;
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wire we_reg, adder_pc, data_out;
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wire [1:0] input_reg;
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wire [4:0] select_a, select_b, select_d;
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wire source_alu;
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wire [3:0] op_code_alu;
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wire mem_we;
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wire [1:0] jmp_pc;
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wire b_pc, alu_not;
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wire [31:0] input_d;
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wire [31:0] output_a, output_b;
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wire [31:0] immediate;
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wire [31:0] pc;
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wire [31:0] new_pc;
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wire [1:0] pc_in;
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wire [31:0] memory_out;
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wire [31:0] pc_store;
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decoder decoder (
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.instruction(instruction),
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.immediate(immediate),
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.we_reg(we_reg),
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.adder_pc(adder_pc),
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.data_out(data_out),
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.input_reg(input_reg),
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.select_a(select_a),
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.select_b(select_b),
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.select_d(select_d),
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.source_alu(source_alu),
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.op_code_alu(op_code_alu),
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.mem_we(mem_we),
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.jmp_pc(jmp_pc),
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.b_pc(b_pc),
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.alu_not(alu_not)
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);
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registers_bank registers_bank (
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.clock(clock),
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.reset(reset),
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.we(we_reg),
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.select_d(select_d),
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.select_a(select_a),
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.select_b(select_b),
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.input_d(input_d),
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.output_a(output_a),
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.output_b(output_b)
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);
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mux2_1 mux2_1_1 (
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.A(output_b),
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.B(immediate),
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.S(source_alu),
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.O(in_b)
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);
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alu alu (
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.input_a(output_a),
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.input_b(in_b),
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.op_code(op_code_alu),
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.out(alu_out)
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);
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mux2_1 #(2) mux2_1_2 (
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.A(jmp_pc),
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.B({alu_out[1], (alu_not ? ~alu_out[0] : alu_out[0])}),
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.S(b_pc),
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.O(pc_in)
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);
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mux4_1 mux4_1_1 (
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.A(pc + 4),
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.B(pc + immediate),
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.C(alu_out),
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.D(0),
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.S(pc_in),
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.O(new_pc)
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);
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program_counter program_counter (
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.clock(clock),
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.reset(clock),
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.new_pc(new_pc),
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.pc(pc)
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);
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instruction uut_instruction (
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.address(pc),
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.instruction(instruction)
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);
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memory memory (
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.clock(clock),
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.reset(reset),
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.we(mem_we),
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.address(alu_out),
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.data_in(output_b),
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.data_out(memory_out)
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);
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mux2_1 mux2_1_3 (
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.A(4),
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.B(alu_out),
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.S(adder_pc),
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.O(pc_store)
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);
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mux4_1 mux4_1_2 (
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.A(pc_store + pc),
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.B(alu_out),
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.C(memory_out),
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.D(0),
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.S(input_reg),
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.O(input_d)
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);
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endmodule
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