14 lines
290 B
Coq
14 lines
290 B
Coq
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module risc_v_cpu_top (input clock, reset,
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output [31:0] out);
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/* You can use the following file as your top layer for your FPGA synthesis */
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risc_v_cpu risc_v_cpu (
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.clock(clock),
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.reset(reset),
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.out(out)
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);
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endmodule
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