Add: archi and comment in top level | Fix: missing var declaration in reg test bench

rtl/risc_v_cpu_top.v

@@ -0,0 +1,13 @@
+module risc_v_cpu_top (input         clock, reset,
+                       output [31:0] out);
+
+    /* You can use the following file as your top layer for your FPGA synthesis */
+
+    risc_v_cpu risc_v_cpu (
+        .clock(clock),
+        .reset(reset),
+        .out(out)
+    );
+
+endmodule
+

tb/tb_registers_bank.v

@@ -2,6 +2,7 @@
 `include "tb_tools.vh"
 
 module tb_registers_bank ();
+    integer     i;
     reg         clk;
     reg         reset;
     reg         we;

tb/tb_tools.vh

@@ -42,4 +42,4 @@
 
 `define next_cycle \
     #1 clk = ~clk; \
-    #1 clk = ~clk;
+    #1 clk = ~clk;