RISC-V_Verilog/Makefile

20 lines
360 B
Makefile
Raw Normal View History

2023-10-11 08:43:36 +00:00
all: simulation
$(MAKE) -C sim $@
debug: simulation
$(MAKE) -C sim $@
simulation:
./scripts/gen_simu_do.sh $(TARGET) $(WAVE)
clean:
rm -rf sim/work
2023-10-26 08:43:00 +00:00
rm -rf work
2023-10-11 08:43:36 +00:00
rm -rf sim/transcript
2023-10-26 08:43:00 +00:00
rm -rf transcript
2023-10-11 08:43:36 +00:00
rm -rf sim/vsim.wlf
rm -rf sim/simu.do
2023-11-20 13:20:42 +00:00
rm -rf tb/test_source_code/**/*.bin
rm -rf tb/test_source_code/**/*.elf
rm -rf tb/test_source_code/**/*.o