brice/RISC-V_Verilog
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Add: risc-v test bubble sort

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This commit is contained in:
brice.boisson
2023-10-26 17:43:00 +09:00
parent d51ea5c4c8
commit 9613e2566e
6 changed files with 124 additions and 56 deletions
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2
Makefile
View File

@@ -9,6 +9,8 @@ simulation:
clean:
rm -rf sim/work
rm -rf work
rm -rf sim/transcript
rm -rf transcript
rm -rf sim/vsim.wlf
rm -rf sim/simu.do

16
rtl/decoder.v
View File

@@ -50,12 +50,12 @@ endfunction
function [3:0] branch_func(input [2:0] func);
begin
case (func)
3'b000 : branch_func = 4'b0001;
3'b001 : branch_func = 4'b0001;
3'b010 : branch_func = 4'b0011;
3'b011 : branch_func = 4'b0011;
3'b100 : branch_func = 4'b0011;
3'b101 : branch_func = 4'b0011;
3'b000 : branch_func = SUB;
3'b001 : branch_func = SUB;
3'b100 : branch_func = SLT;
3'b101 : branch_func = SLT;
3'b110 : branch_func = SLTU;
3'b111 : branch_func = SLTU;
default : branch_func = 4'b0000;
endcase
end
@@ -66,10 +66,10 @@ function branch_not(input [2:0] func);
case (func)
3'b000 : branch_not = 1;
3'b001 : branch_not = 0;
3'b010 : branch_not = 0;
3'b011 : branch_not = 1;
3'b100 : branch_not = 0;
3'b101 : branch_not = 1;
3'b110 : branch_not = 0;
3'b111 : branch_not = 1;
default : branch_not = 0;
endcase
end

2
rtl/risc_v_cpu.v
View File

@@ -69,7 +69,7 @@ module risc_v_cpu (input clock, reset,
mux2_1 #(2) mux2_pc_sel_branch (
.in_1(pc_is_branch),
.in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 0 ? 1'b1 : 1'b0))}),
.in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}),
.sel(pc_is_jmp),
.out(pc_sel_in)
);

2
scripts/gen_simu_do.sh
View File

@@ -26,7 +26,7 @@ vlog ../tb/tb_'"$FILE_NAME"'.v
' >> ./sim/simu.do
echo 'vsim tb_'"$FILE_NAME"'
add wave -radix unsigned *' >> ./sim/simu.do
' >> ./sim/simu.do
# loop through all arguments from $3

1
tb/tb_registers_bank.v
View File

@@ -4,7 +4,6 @@
module tb_registers_bank ();
reg clk;
reg reset;
integer i;
reg we;
reg [4:0] sel_in;
reg [4:0] sel_out_a;

157
tb/tb_risc_v_cpu.v
View File

@@ -186,30 +186,23 @@ module tb_risc_v_cpu ();
clk = 1'b0;
/* BUBBLE SORT
int len = 10;
int array[] = {10, 9, 8, 7, 6, 5, 4, 3, 2, 1};
for (int i = len - 1; i > 0; i--)
{
for (int j = 0; j < i; j++)
{
if (array[j] > array[j + 1])
{
int temp = array[j];
array[j] = array[j + 1];
array[j + 1] = temp;
}
}
}
LOAD MEM[R[2] + 0] to R[3]
LOAD MEM[R[2] + 1] to R[4]
JUMP TO R[2]++ if R[4] >= R[3]
STR R[4] to MEM[R[2] + 0]
STR R[3] to MEM[R[2] + 1]
R[2]++
JUM to -12 if R[2] < R[1]
R[1]--
JMP if R[1] == 0 FIRST LINE
*/
/* BUBBLE SORT */
/* ADDi $10, R[0], R[1] - R[1] = 10 */
/* ADDi $9, R[0], R[1] - R[1] = 9 */
/* "000000001010_00000_000_00001_0010000" */
risc_v_cpu.uut_instruction.memory[0] = 8'b10010000;
risc_v_cpu.uut_instruction.memory[1] = 8'b00000000;
risc_v_cpu.uut_instruction.memory[2] = 8'b10100000;
risc_v_cpu.uut_instruction.memory[2] = 8'b10010000;
risc_v_cpu.uut_instruction.memory[3] = 8'b00000000;
/* ADDi $10, R[0], R[2] - R[2] = 10 */
@@ -233,46 +226,120 @@ module tb_risc_v_cpu ();
risc_v_cpu.uut_instruction.memory[14] = 8'b00100000;
risc_v_cpu.uut_instruction.memory[15] = 8'b00000000;
/* ADDi $-1, R[2], R[2] - R[2] = 9 */
/* ADDi $-1, R[2], R[2] - R[2] = R[2] - 1 */
/* "111111111111_00010_000_00010_0010000" */
risc_v_cpu.uut_instruction.memory[16] = 8'b00010000;
risc_v_cpu.uut_instruction.memory[17] = 8'b00000001;
risc_v_cpu.uut_instruction.memory[18] = 8'b11110001;
risc_v_cpu.uut_instruction.memory[19] = 8'b11111111;
/* ADDi $1, R[3], R[3] - R[3] = 1 */
/* ADDi $1, R[3], R[3] - R[3] = R[3] + 1 */
/* "000000000001_00011_000_00011_0010000" */
risc_v_cpu.uut_instruction.memory[20] = 8'b10010000;
risc_v_cpu.uut_instruction.memory[21] = 8'b10000001;
risc_v_cpu.uut_instruction.memory[22] = 8'b00010001;
risc_v_cpu.uut_instruction.memory[23] = 8'b00000000;
/* BNE -8, R[0], R[2] - R[2] = 9 */
/* "1111111_00010_00000_001_10111_1100000" */
risc_v_cpu.uut_instruction.memory[24] = 8'b01100000;
risc_v_cpu.uut_instruction.memory[25] = 8'b00011100;
risc_v_cpu.uut_instruction.memory[26] = 8'b00100000;
risc_v_cpu.uut_instruction.memory[27] = 8'b11111110;
/* STR $0, R[3], R[2], MEM[R[3]] = 10 */
/* "0000000_00010_00011_000_00000_0100000" */
risc_v_cpu.uut_instruction.memory[24] = 8'b00100000;
risc_v_cpu.uut_instruction.memory[25] = 8'b10000000;
risc_v_cpu.uut_instruction.memory[26] = 8'b00100001;
risc_v_cpu.uut_instruction.memory[27] = 8'b00000000;
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
`next_cycle
/* BNE -12, R[0], R[2] - PC = PC - 12 */
/* "1111111_00010_00000_001_10100_1100000" */
risc_v_cpu.uut_instruction.memory[28] = 8'b01100000;
risc_v_cpu.uut_instruction.memory[29] = 8'b00011010;
risc_v_cpu.uut_instruction.memory[30] = 8'b00100000;
risc_v_cpu.uut_instruction.memory[31] = 8'b11111110;
/* ADDi $0, R[0], R[2] - R[2] = 0 */
/* "000000000000_00000_000_00010_0010000" */
risc_v_cpu.uut_instruction.memory[32] = 8'b00010000;
risc_v_cpu.uut_instruction.memory[33] = 8'b00000001;
risc_v_cpu.uut_instruction.memory[34] = 8'b00000000;
risc_v_cpu.uut_instruction.memory[35] = 8'b00000000;
/* LOAD MEM[R[2] + 0], R[3] - R[3] = 10 */
/* "000000000000_00010_000_00011_0000000" */
risc_v_cpu.uut_instruction.memory[36] = 8'b10000000;
risc_v_cpu.uut_instruction.memory[37] = 8'b00000001;
risc_v_cpu.uut_instruction.memory[38] = 8'b00000001;
risc_v_cpu.uut_instruction.memory[39] = 8'b00000000;
/* LOAD MEM[R[2] + 1], R[4] - R[4] = 9 */
/* "000000000001_00010_000_00100_0000000" */
risc_v_cpu.uut_instruction.memory[40] = 8'b00000000;
risc_v_cpu.uut_instruction.memory[41] = 8'b00000010;
risc_v_cpu.uut_instruction.memory[42] = 8'b00010001;
risc_v_cpu.uut_instruction.memory[43] = 8'b00000000;
/* BNE 12, R[4], R[3] - PC = PC + 12 */
/* "0000000_00100_00011_100_01100_1100000" */
risc_v_cpu.uut_instruction.memory[44] = 8'b01100000;
risc_v_cpu.uut_instruction.memory[45] = 8'b11000110;
risc_v_cpu.uut_instruction.memory[46] = 8'b01000001;
risc_v_cpu.uut_instruction.memory[47] = 8'b00000000;
/* STR $0, R[2], R[4], MEM[R[2]] = 9 */
/* "0000000_00100_00010_000_00000_0100000" */
risc_v_cpu.uut_instruction.memory[48] = 8'b00100000;
risc_v_cpu.uut_instruction.memory[49] = 8'b00000000;
risc_v_cpu.uut_instruction.memory[50] = 8'b01000001;
risc_v_cpu.uut_instruction.memory[51] = 8'b00000000;
/* STR $1, R[2], R[3], MEM[R[2]] = 9 */
/* "0000000_00011_00010_000_00001_0100000" */
risc_v_cpu.uut_instruction.memory[52] = 8'b10100000;
risc_v_cpu.uut_instruction.memory[53] = 8'b00000000;
risc_v_cpu.uut_instruction.memory[54] = 8'b00110001;
risc_v_cpu.uut_instruction.memory[55] = 8'b00000000;
/* ADDi $1, R[2], R[2] - R[2] = R[2] + 1 */
/* "000000000001_00010_000_00010_0010000" */
risc_v_cpu.uut_instruction.memory[56] = 8'b00010000;
risc_v_cpu.uut_instruction.memory[57] = 8'b00000001;
risc_v_cpu.uut_instruction.memory[58] = 8'b00010001;
risc_v_cpu.uut_instruction.memory[59] = 8'b00000000;
/* BNE -xx, R[1], R[2] - PC = PC - 8 */
/* "1111111_00010_00001_001_01000_1100000" */
risc_v_cpu.uut_instruction.memory[60] = 8'b01100000;
risc_v_cpu.uut_instruction.memory[61] = 8'b10010100;
risc_v_cpu.uut_instruction.memory[62] = 8'b00100000;
risc_v_cpu.uut_instruction.memory[63] = 8'b11111110;
/* ADDi $-1, R[1], R[1] - R[1] = R[1] - 1 */
/* "111111111111_00001_000_00001_0010000" */
risc_v_cpu.uut_instruction.memory[64] = 8'b10010000;
risc_v_cpu.uut_instruction.memory[65] = 8'b10000000;
risc_v_cpu.uut_instruction.memory[66] = 8'b11110000;
risc_v_cpu.uut_instruction.memory[67] = 8'b11111111;
/* BNE -36, R[0], R[1] - PC = PC - 8 */
/* "1111111_00001_00000_001_100000_1100000" */
risc_v_cpu.uut_instruction.memory[68] = 8'b01100000;
risc_v_cpu.uut_instruction.memory[69] = 8'b10011110;
risc_v_cpu.uut_instruction.memory[70] = 8'b00000000;
risc_v_cpu.uut_instruction.memory[71] = 8'b11111100;
for (i = 0; i < 387; i = i + 1) begin
`next_cycle
end
`assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.memory.memory[0], 1)
`assert_no_wait("BUBBLE SORT - MEM[1]: 2", risc_v_cpu.memory.memory[1], 2)
`assert_no_wait("BUBBLE SORT - MEM[2]: 3", risc_v_cpu.memory.memory[2], 3)
`assert_no_wait("BUBBLE SORT - MEM[3]: 4", risc_v_cpu.memory.memory[3], 4)
`assert_no_wait("BUBBLE SORT - MEM[4]: 5", risc_v_cpu.memory.memory[4], 5)
`assert_no_wait("BUBBLE SORT - MEM[5]: 6", risc_v_cpu.memory.memory[5], 6)
`assert_no_wait("BUBBLE SORT - MEM[6]: 7", risc_v_cpu.memory.memory[6], 7)
`assert_no_wait("BUBBLE SORT - MEM[7]: 8", risc_v_cpu.memory.memory[7], 8)
`assert_no_wait("BUBBLE SORT - MEM[8]: 9", risc_v_cpu.memory.memory[8], 9)
`assert_no_wait("BUBBLE SORT - MEM[9]: 10", risc_v_cpu.memory.memory[9], 10)
`assert_no_wait("BUBBLE SORT - PROGRAM EXITED - PC: 76", risc_v_cpu.program_counter.pc_addr, 76)
`end_message
end