RISC-V_Verilog/Makefile

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Makefile
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all: simulation
$(MAKE) -C sim $@
debug: simulation
$(MAKE) -C sim $@
simulation:
./scripts/gen_simu_do.sh $(TARGET) $(WAVE)
clean:
rm -rf sim/work
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rm -rf work
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rm -rf sim/transcript
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rm -rf transcript
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rm -rf sim/vsim.wlf
rm -rf sim/simu.do
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rm -rf tb/test_source_code/**/*.bin
rm -rf tb/test_source_code/**/*.elf
rm -rf tb/test_source_code/**/*.o
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rm -rf tb/test_source_code/**/*.tmp