Merge pull request #5 from BriceBoisson/test-3
Add: new test source code + Fix: gen_bin script and bin path
This commit is contained in:
BOISSON Brice
GitHub
commit
0fa44c1830
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@ -12,9 +12,9 @@ test_file = []
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def get_test(test, instr_addr, final = False):
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result = ""
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pattern_r = re.compile(r'R\[(\d+)\]=(\d+)')
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pattern_r = re.compile(r'R\[(\d+)\]=([+-]?\d+)')
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pattern_pc = re.compile(r'PC=(\d+)')
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pattern_mem = re.compile(r'MEM\[(\d+)\]=(\d+)')
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pattern_mem = re.compile(r'MEM\[(\d+)\]=([+-]?\d+)')
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# Use the patterns to search for matches in the input string
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match_r = pattern_r.search(test)
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@ -40,12 +40,14 @@ def get_test(test, instr_addr, final = False):
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instr_addr = 0
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for line in Lines:
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if line.isspace() or ':' in line or line[0] == '#':
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if line.isspace() or ':' in line or line[0] == '#' or line[0:2] == '/*' or line[0:2] == '*/' or line[0:2] == ' *':
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continue
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elif '#' in line:
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print(line)
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tests = re.split(r'\s|,', line[line.find('#') + 1:])
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for test in tests:
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new_test = get_test(test, instr_addr)
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print(new_test)
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if new_test != "":
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test_file.append(new_test)
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instr_addr += 4
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@ -18,10 +18,10 @@ NAME=$(basename $1)
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NAME=${NAME%.*}
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FOLDER=$(dirname $1)
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riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${FOLDER}/${NAME}.S -o ${NAME}.o
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riscv32-unknown-elf-ld -Ttext=0x0 ${NAME}.o -o ${NAME}.elf
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riscv32-unknown-elf-objcopy -O binary ${NAME}.elf ${NAME}.bin
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riscv32-unknown-elf-as -march=rv32i -mabi=ilp32 ${FOLDER}/${NAME}.S -o test.o
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riscv32-unknown-elf-ld -Ttext=0x0 test.o -o test.elf
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riscv32-unknown-elf-objcopy -O binary test.elf test.bin
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rm -rf ${NAME}.o ${NAME}.elf
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rm -rf test.o test.elf
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exit 0
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@ -117,29 +117,29 @@ module tb_risc_v_cpu ();
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`next_cycle
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if (test[curent_addr][5:0] != 6'b111111) begin
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if (test[curent_addr][5:0] < 6'b100000) begin
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`assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][5:0], risc_v_cpu.registers_bank.registers[test[curent_addr][4:0]], test[curent_addr][37:6])
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`assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][5:0], test[curent_addr][37:6], risc_v_cpu.registers_bank.registers[test[curent_addr][4:0]])
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end else if (test[curent_addr][5:0] == 6'b100000) begin
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`assert_no_wait_pc("RUNTIME", curent_addr, risc_v_cpu.program_counter.pc_addr, test[curent_addr][37:6])
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`assert_no_wait_pc("RUNTIME", curent_addr, test[curent_addr][37:6], risc_v_cpu.program_counter.pc_addr)
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end else if (test[curent_addr][5:0] > 6'b100000) begin
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`assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][5:0], risc_v_cpu.memory.memory[test[curent_addr][5:0]], test[curent_addr][37:6])
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`assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][5:0], test[curent_addr][37:6], risc_v_cpu.memory.memory[test[curent_addr][5:0]])
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end
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end
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if (test[curent_addr][43:38] != 6'b111111) begin
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if (test[curent_addr][43:38] < 6'b100000) begin
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`assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][43:38], risc_v_cpu.registers_bank.registers[test[curent_addr][42:38]], test[curent_addr][75:44])
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`assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][43:38], test[curent_addr][75:44], risc_v_cpu.registers_bank.registers[test[curent_addr][42:38]])
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end else if (test[curent_addr][43:38] == 6'b100000) begin
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`assert_no_wait_pc("RUNTIME", curent_addr, risc_v_cpu.program_counter.pc_addr, test[curent_addr][75:44])
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`assert_no_wait_pc("RUNTIME", curent_addr, test[curent_addr][75:44], risc_v_cpu.program_counter.pc_addr)
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end else if (test[curent_addr][43:38] > 6'b100000) begin
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`assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][43:38], risc_v_cpu.memory.memory[test[curent_addr][43:38]], test[curent_addr][75:44])
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`assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][43:38], test[curent_addr][75:44], risc_v_cpu.memory.memory[test[curent_addr][43:38]])
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end
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end
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if (test[curent_addr][81:76] != 6'b111111) begin
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if (test[curent_addr][81:76] < 6'b100000) begin
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`assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][81:76], risc_v_cpu.registers_bank.registers[test[curent_addr][80:76]], test[curent_addr][81:76])
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`assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][81:76], test[curent_addr][81:76], risc_v_cpu.registers_bank.registers[test[curent_addr][80:76]])
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end else if (test[curent_addr][81:76] == 6'b100000) begin
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`assert_no_wait_pc("RUNTIME", curent_addr, risc_v_cpu.program_counter.pc_addr, test[curent_addr][113:83])
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`assert_no_wait_pc("RUNTIME", curent_addr, test[curent_addr][113:83], risc_v_cpu.program_counter.pc_addr)
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end else if (test[curent_addr][81:76] > 6'b100000) begin
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`assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][81:76], risc_v_cpu.memory.memory[test[curent_addr][81:76]], test[curent_addr][81:76])
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`assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][81:76], test[curent_addr][81:76], risc_v_cpu.memory.memory[test[curent_addr][81:76]])
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end
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end
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end
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@ -163,11 +163,11 @@ module tb_risc_v_cpu ();
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end
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if (reg_number < 6'b100000) begin
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`assert_no_wait_reg("FINAL", 1'bx, reg_number, risc_v_cpu.registers_bank.registers[reg_number[4:0]], reg_test_value)
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`assert_no_wait_reg("FINAL", 1'bx, reg_number, reg_test_value, risc_v_cpu.registers_bank.registers[reg_number[4:0]])
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end else if (reg_number == 6'b100000) begin
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`assert_no_wait_pc("FINAL", 1'bx, risc_v_cpu.program_counter.pc_addr, reg_test_value)
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`assert_no_wait_pc("FINAL", 1'bx, reg_test_value, risc_v_cpu.program_counter.pc_addr)
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end else if (reg_number > 6'b100000) begin
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`assert_no_wait_mem("FINAL", 1'bx, reg_number, risc_v_cpu.memory.memory[test[curent_addr][5:0]], reg_test_value)
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`assert_no_wait_mem("FINAL", 1'bx, reg_number, reg_test_value, risc_v_cpu.memory.memory[test[curent_addr][5:0]])
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end
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end
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@ -0,0 +1,26 @@
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/*
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* 0:zero, 1:ra, 2:sp, 3:gp, 4:tp, 5:t0-2, 8:s0/fp
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* 9:s1, 10:a0-7, 18:s2-11, 28:t3-6
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*/
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/* addi dest, reg1, imm */
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addi a0, zero, 10 # R[10]=10
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addi a1, zero, 1 # R[11]=1
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/* addi dest, reg1, reg2 */
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add a2, a0, a1 # R[12]=11
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/* sub dest, reg1, reg2 - reg1 - reg2 */
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sub a1, a2, a0 # R[11]=1
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/* add dest, reg1, reg2 - reg1 & reg2 */
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and a2, zero, a1 # R[12]=0
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/* or dest, reg1, reg2 - reg1 | reg2 */
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or a2, a0, a1 # R[12]=11
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/* xor dest, reg1, reg2 - reg1 ^ reg2 */
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xor a0, a2, a1 # R[10]=10
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/* li dest, imm */
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li a0, -10 # R[10]=-10
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/* mv dest, reg1 */
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mv a1, a0 # R[11]=-10
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/* neg dest, reg1 */
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neg a1, a2 # R[11]=-11
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# R[0]=0
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