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Add: new test source code + Fix: gen_bin script and bin path #5

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BriceBoisson merged 1 commits from test-3 into main 2023-11-25 14:19:04 +00:00
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BriceBoisson commented 2023-11-25 14:18:54 +00:00 (Migrated from github.com)
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Reference: brice/RISC-V_Verilog#5
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