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RISC-V_Verilog
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Add: first test

This commit is contained in:
brice.boisson 2023-11-20 22:30:19 +09:00
parent 99399cd9b3
commit 1f9a8ceebf
2 changed files with 11 additions and 6 deletions
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8
tb/tb_risc_v_cpu-dyn.v
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@ -31,7 +31,7 @@ module tb_risc_v_cpu ();
/* Loading Test From File */ /* Loading Test From File */
/* Loading Binary File */ /* Loading Binary File */
bin_file_inputs = $fopen("/home/brice/Code/RISC-V_VERILOG/tb/test.bin", "r"); bin_file_inputs = $fopen("./../tb/test_source_code/tb_riscv_cpu/test.bin", "r");
if (bin_file_inputs == 0) begin if (bin_file_inputs == 0) begin
$display("data_file handle was NULL"); $display("data_file handle was NULL");
$finish; $finish;
@ -59,10 +59,6 @@ module tb_risc_v_cpu ();
i = i + 4; i = i + 4;
end end
end end
`assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[0], 8'b00000000)
`assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[1], 8'b11000101)
`assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[2], 8'b10000111)
`assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.uut_instruction.memory[3], 8'b10110011)
for (i = 0; i < 100; i = i + 1) begin for (i = 0; i < 100; i = i + 1) begin
`next_cycle `next_cycle
@ -70,7 +66,7 @@ module tb_risc_v_cpu ();
end end
// final test // final test
`assert_no_wait("BUBBLE SORT - MEM[0]: 1", risc_v_cpu.memory.memory[0], 8'b00000000) `assert_no_wait("FOR LOOP - REG[5]: 1", risc_v_cpu.registers_bank.registers[5], 32'b1010)
`end_message `end_message
end end

9
tb/test_source_code/tb_riscv_cpu/test.S Normal file
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@ -0,0 +1,9 @@
# t0 = 0
li t0, 0
li t2, 10
loop_head:
bge t0, t2, loop_end
# Repeated code goes here
addi t0, t0, 1
j loop_head
loop_end: