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RISC-V_Verilog
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Fix: clean name [2]

This commit is contained in:
brice.boisson 2023-10-23 11:47:43 +09:00
parent c1a099c75d
commit 2c9abe91af
2 changed files with 36 additions and 42 deletions
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44
rtl/decoder.v
View File

@ -6,8 +6,8 @@ module decoder (input [31:0] instruction,
output reg alu_src, output reg alu_src,
output reg [3:0] alu_func, output reg [3:0] alu_func,
output reg mem_we, output reg mem_we,
output reg [1:0] jmp_pc, output reg [1:0] pc_is_branch,
output reg b_pc, alu_not); output reg pc_is_jmp, alu_not);
`include "op_code.vh" `include "op_code.vh"
@ -88,8 +88,8 @@ endfunction
alu_src = 0; alu_src = 0;
alu_func = get_alu_func(instruction[14:12], instruction[30]); alu_func = get_alu_func(instruction[14:12], instruction[30]);
mem_we = 0; mem_we = 0;
jmp_pc = 2'b00; pc_is_branch = 2'b00;
b_pc = 0; pc_is_jmp = 0;
alu_not = 0; alu_not = 0;
end end
OP_IMM : begin // OP-IMM - Addi, ... OP_IMM : begin // OP-IMM - Addi, ...
@ -103,8 +103,8 @@ endfunction
alu_src = 1; alu_src = 1;
alu_func = get_alu_func_imm(instruction[14:12], instruction[30]); alu_func = get_alu_func_imm(instruction[14:12], instruction[30]);
mem_we = 0; mem_we = 0;
jmp_pc = 2'b00; pc_is_branch = 2'b00;
b_pc = 0; pc_is_jmp = 0;
alu_not = 0; alu_not = 0;
end end
LOAD : begin // LOAD - Lw, ... LOAD : begin // LOAD - Lw, ...
@ -118,8 +118,8 @@ endfunction
alu_src = 1; alu_src = 1;
alu_func = 3'b000; alu_func = 3'b000;
mem_we = 0; mem_we = 0;
jmp_pc = 2'b00; pc_is_branch = 2'b00;
b_pc = 0; pc_is_jmp = 0;
alu_not = 0; alu_not = 0;
end end
STORE : begin // STORE - Sw, ... STORE : begin // STORE - Sw, ...
@ -133,8 +133,8 @@ endfunction
alu_src = 1; alu_src = 1;
alu_func = 3'b000; alu_func = 3'b000;
mem_we = 1; mem_we = 1;
jmp_pc = 2'b00; pc_is_branch = 2'b00;
b_pc = 0; pc_is_jmp = 0;
alu_not = 0; alu_not = 0;
end end
BRANCH : begin // BRANCH - Beq, ... BRANCH : begin // BRANCH - Beq, ...
@ -148,8 +148,8 @@ endfunction
alu_src = 0; alu_src = 0;
alu_func = branch_op_code(instruction[14:12]); alu_func = branch_op_code(instruction[14:12]);
mem_we = 0; mem_we = 0;
jmp_pc = 2'b00; pc_is_branch = 2'b00;
b_pc = 1; pc_is_jmp = 1;
alu_not = branch_not(instruction[14:12]); alu_not = branch_not(instruction[14:12]);
end end
JAL : begin // JUMP - Jal JAL : begin // JUMP - Jal
@ -163,8 +163,8 @@ endfunction
alu_src = 0; alu_src = 0;
alu_func = 3'b000; alu_func = 3'b000;
mem_we = 0; mem_we = 0;
jmp_pc = 2'b01; pc_is_branch = 2'b01;
b_pc = 0; pc_is_jmp = 0;
alu_not = 0; alu_not = 0;
end end
JALR : begin // JUMP REG - Jalr JALR : begin // JUMP REG - Jalr
@ -178,8 +178,8 @@ endfunction
alu_src = 0; alu_src = 0;
alu_func = 3'b000; alu_func = 3'b000;
mem_we = 0; mem_we = 0;
jmp_pc = 2'b10; pc_is_branch = 2'b10;
b_pc = 0; pc_is_jmp = 0;
alu_not = 0; alu_not = 0;
end end
LUI : begin // LUI - lui LUI : begin // LUI - lui
@ -192,8 +192,8 @@ endfunction
alu_src = 1; alu_src = 1;
alu_func = 3'b000; alu_func = 3'b000;
mem_we = 0; mem_we = 0;
jmp_pc = 2'b00; pc_is_branch = 2'b00;
b_pc = 0; pc_is_jmp = 0;
alu_not = 0; alu_not = 0;
end end
AUIPC : begin // AUIPC - auipc AUIPC : begin // AUIPC - auipc
@ -206,8 +206,8 @@ endfunction
alu_src = 1; alu_src = 1;
alu_func = 3'b000; alu_func = 3'b000;
mem_we = 0; mem_we = 0;
jmp_pc = 2'b00; pc_is_branch = 2'b00;
b_pc = 0; pc_is_jmp = 0;
alu_not = 0; alu_not = 0;
end end
default : begin // NOP default : begin // NOP
@ -220,8 +220,8 @@ endfunction
alu_src = 0; alu_src = 0;
alu_func = 3'b000; alu_func = 3'b000;
mem_we = 0; mem_we = 0;
jmp_pc = 2'b00; pc_is_branch = 2'b00;
b_pc = 0; pc_is_jmp = 0;
alu_not = 0; alu_not = 0;
end end
endcase endcase

32
rtl/risc_v_cpu.v
View File

@ -1,30 +1,24 @@
module risc_v_cpu (input clock, reset, output [31:0] out); module risc_v_cpu (input clock, reset, output [31:0] out);
wire alu_src, alu_not; wire [31:0] instruction;
wire [3:0] alu_func;
wire [31:0] alu_in_b, alu_out; wire [31:0] imm;
wire reg_we; wire reg_we;
wire [1:0] reg_sel_data_in; wire [1:0] reg_sel_data_in;
wire [4:0] reg_sel_out_a, reg_sel_out_b, reg_sel_in; wire [4:0] reg_sel_out_a, reg_sel_out_b, reg_sel_in;
wire [31:0] reg_data_out_a, reg_data_out_b, reg_data_in; wire [31:0] reg_data_out_a, reg_data_out_b, reg_data_in;
wire [31:0] instruction; wire alu_src, alu_not;
wire [3:0] alu_func;
wire [31:0] alu_in_b, alu_out;
wire mem_we; wire mem_we;
wire [31:0] mem_out; wire [31:0] mem_out;
wire [1:0] jmp_pc; wire pc_is_jmp;
wire b_pc; wire [1:0] pc_is_branch, pc_sel_in;
wire [31:0] pc_addr, pc_new_addr;
wire [31:0] imm;
wire [1:0] pc_sel_in;
wire [31:0] pc_addr;
wire [31:0] pc_new_addr;
wire [31:0] pc_store;
decoder decoder ( decoder decoder (
.instruction(instruction), .instruction(instruction),
@ -37,8 +31,8 @@ module risc_v_cpu (input clock, reset, output [31:0] out);
.alu_src(alu_src), .alu_src(alu_src),
.alu_func(alu_func), .alu_func(alu_func),
.mem_we(mem_we), .mem_we(mem_we),
.jmp_pc(jmp_pc), .pc_is_branch(pc_is_branch),
.b_pc(b_pc), .pc_is_jmp(pc_is_jmp),
.alu_not(alu_not) .alu_not(alu_not)
); );
@ -69,9 +63,9 @@ module risc_v_cpu (input clock, reset, output [31:0] out);
); );
mux2_1 #(2) mux2_1_2 ( mux2_1 #(2) mux2_1_2 (
.A(jmp_pc), .A(pc_is_branch),
.B({alu_out[1], (alu_not ? ~alu_out[0] : alu_out[0])}), .B({alu_out[1], (alu_not ? ~alu_out[0] : alu_out[0])}),
.S(b_pc), .S(pc_is_jmp),
.O(pc_sel_in) .O(pc_sel_in)
); );