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RISC-V_Verilog
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Add: debug command in Makefile

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brice.boisson 2023-11-29 11:14:42 +09:00
parent fb95d74cd7
commit 3007868c1a
1 changed files with 4 additions and 1 deletions
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@ -13,10 +13,13 @@ This CPU will implement the RV32I ISA, with the following goals:
Use the command : ```make TARGET=<test_bench>-<sub_test>``` Use the command : ```make TARGET=<test_bench>-<sub_test>```
With `test_bench` among the listed test bench in the `tb` directory and `sub_test` a source code file in the `tb/test_source_code/tb_<test_bench>` directory. \ With `test_bench` among the listed test bench in the `tb` directory and `sub_test` a source code file in the `tb/test_source_code/tb_<test_bench>` directory. \
Example: `make TARGET=risc_v_cpu-test` Example: `make TARGET=risc_v_cpu-alu_instruction`
You can remove the dash and `sub_test` argument to run only the non source code based test. \ You can remove the dash and `sub_test` argument to run only the non source code based test. \
Example: `make TARGET=risc_v_cpu` Example: `make TARGET=risc_v_cpu`
Or use `all` as a `sub_test` to run all test associated to a `test_bench`. \ Or use `all` as a `sub_test` to run all test associated to a `test_bench`. \
Example: `make TARGET=risc_v_cpu-all` Example: `make TARGET=risc_v_cpu-all`
You can add the flag `debug` at the end of the command to open ModelSim interface. \
Example: `make TARGET=risc_v_cpu-alu_instruction debug`