Fix: reset edge

rtl/instruction.v

@@ -1,8 +1,49 @@
 module instruction (input [31:0] address,
                        output [31:0] instruction);
     
-    reg [63:0] memory [31:0];
+    reg [31:0] memory [63:0];
+
+    // ADDi $1, R[0], R[6]
+    // "000000000001_00000_000_00110_0010000"
+    assign memory[0] = 32'b00000000000100000000001100010000;
+
+    // ADDi $0, R[0], R[7]
+    // "000000000000_00000_000_00111_0010000"
+    assign memory[4] = 32'b00000000000000000000001110010000;
+
+    // ADDi $0, R[6],  R[8]
+    // "000000000000_00110_000_01000_0010000"
+    assign memory[8] = 32'b00000000000000110000010000010000;
+
+    // ADD R[7], R[6], R[6]
+    // "0000000_00111_00110_000_00110_0110000"
+    assign memory[12] = 32'b00000000011100110000001100110000;
+
+    // ADDi $0, R[8], R[7]
+    // "000000000000_01000_000_00111_0010000"
+    assign memory[16] = 32'b00000000000001000000001110010000;
+
+    // JUMP 
+    // 111111111111_11111_101_00111_1101100
+    assign memory[20] = 32'b11111111111111111101001111101100;
 
     assign instruction = memory[address];
 
 endmodule
+
+// -- result(1) := "00000000001100110000010000010000";
+
+// -- "000000000000_00000_000_00110_0010000"
+// result(0) := "00000000000100000000001100010000";
+// -- "000000000001_00000_000_00111_0010000"
+// result(1) := "00000000000000000000001110010000";
+
+// -- "000000000000_00110_000_01000_0010000"
+// result(2) := "00000000000000110000010000010000";
+// -- "0000000_00111_00110_000_00110_0110000"
+// result(3) := "00000000011100110000001100110000";
+// -- "000000000000_01000_000_00111_0010000"
+// result(4) := "00000000000001000000001110010000";
+
+// -- 111111111111_11111_110_00111_1101100
+// result(5) := "11111111111111111101001111101100";

rtl/memory.v

@@ -6,7 +6,7 @@ module memory (input clock, reset,
     
     reg [63:0] memory [31:0];
 
-    always @(posedge clock, reset) begin
+    always @(posedge clock, posedge reset) begin
         if (reset == 1)
             memory[0] <= 32'b0;
         else if (we == 1)

rtl/mux4_1.v

@@ -3,7 +3,7 @@ module mux4_1 #(parameter BUS_SIZE = 32)
                 input [1:0] S,
                 output [BUS_SIZE - 1:0] O);
     
-    assign O = S[0] ? (S[1] ? D : C)
-                    : (S[1] ? B : A);
+    assign O = S[1] ? (S[0] ? D : C)
+                    : (S[0] ? B : A);
 
 endmodule

rtl/program_counter.v

@@ -2,8 +2,8 @@ module program_counter (input clock, reset,
            input [31:0] new_pc,
            output reg [31:0] pc);
     
-    always @ (posedge clock, reset) begin
-        if (reset == 1)
+    always @ (posedge clock, posedge reset) begin
+        if (reset == 1'b1)
             pc <= 32'b0;
         else
             pc <= new_pc;

rtl/registers_bank.v

@@ -5,7 +5,30 @@ module registers_bank (input clock, reset, we,
     
     reg [31:0] registers[31:0];
 
-    always @(posedge clock, reset) begin
+    assign registers[0] = 32'b0;
+    assign registers[1] = 32'b0;
+    assign registers[2] = 32'b0;
+    assign registers[3] = 32'b0;
+    assign registers[4] = 32'b0;
+    assign registers[5] = 32'b0;
+    assign registers[6] = 32'b0;
+    assign registers[7] = 32'b0;
+    assign registers[8] = 32'b0;
+    assign registers[9] = 32'b0;
+    assign registers[10] = 32'b0;
+    assign registers[11] = 32'b0;
+    assign registers[12] = 32'b0;
+    assign registers[13] = 32'b0;
+    assign registers[14] = 32'b0;
+    assign registers[15] = 32'b0;
+    assign registers[16] = 32'b0;
+    assign registers[17] = 32'b0;
+    assign registers[18] = 32'b0;
+    assign registers[19] = 32'b0;
+    assign registers[20] = 32'b0;
+    assign registers[21] = 32'b0;
+    
+    always @(posedge clock, posedge reset) begin
         if (reset == 1)
             registers[0] <= 32'b0;
         else if (we == 1)

rtl/risc_v_cpu.v

@@ -89,7 +89,7 @@ module risc_v_cpu (input clock, reset, output [31:0] out);
 
     program_counter program_counter (
         .clock(clock),
-        .reset(clock),
+        .reset(reset),
         .new_pc(new_pc),
         .pc(pc)
     );

tb/tb_risc_v_cpu.v

@@ -1,6 +1,8 @@
 `timescale 1ns / 1ps
 
 module tb_risc_v_cpu ();
+integer i;
+
 // Clock and reset signals
 reg clk;
 reg reset;
@@ -15,12 +17,6 @@ risc_v_cpu risc_v_cpu (
     .out(out)
 );
 
-// generate the clock
-initial begin
-    clk = 1'b0;
-    forever #1 clk = ~clk;
-end
-
 // Generate the reset
 initial begin
     reset = 1'b1;
@@ -28,4 +24,13 @@ initial begin
     reset = 1'b0;
 end
 
+
+// generate the clock
+initial begin
+    clk = 1'b0;
+    for (i = 0; i < 100; i = i + 1) begin
+        #1 clk = ~clk;
+    end
+end
+
 endmodule : tb_risc_v_cpu