Add: tb registers bank

This commit is contained in:
brice.boisson 2023-10-24 20:08:36 +09:00
parent ecfb4a9cc5
commit 7c1a871e99
3 changed files with 129 additions and 1 deletions

53
tb/tb_mux4_1.v Normal file
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`timescale 1ns / 1ps
`include "tb_tools.vh"
module tb_mux4_1 ();
reg [1:0] sel;
reg [31:0] in_1;
reg [31:0] in_2;
reg [31:0] in_3;
reg [31:0] in_4;
wire [31:0] out;
mux4_1 mux (
.in_1(in_1),
.in_2(in_2),
.in_3(in_3),
.in_4(in_4),
.sel(sel),
.out(out)
);
initial begin
in_1 = 1'b0;
in_2 = 1'b0;
in_3 = 1'b0;
in_4 = 1'b0;
sel = 2'b00;
`assert("mux in_1: 0, in_2: 0, in_3: 0, in_4: 0, sel: 0", out, 0)
in_1 = 1'b1;
`assert("mux in_1: 1, in_2: 0, in_3: 0, in_4: 0, sel: 0", out, 1)
sel = 2'b01;
`assert("mux in_1: 1, in_2: 0, in_3: 0, in_4: 0, sel: 1", out, 0)
in_2 = 1'b1;
`assert("mux in_1: 1, in_2: 1, in_3: 0, in_4: 0, sel: 1", out, 1)
sel = 2'b10;
`assert("mux in_1: 1, in_2: 0, in_3: 0, in_4: 0, sel: 2", out, 0)
in_3 = 1'b1;
`assert("mux in_1: 1, in_2: 1, in_3: 1, in_4: 0, sel: 2", out, 1)
sel = 2'b11;
`assert("mux in_1: 1, in_2: 0, in_3: 1, in_4: 0, sel: 3", out, 0)
in_4 = 1'b1;
`assert("mux in_1: 1, in_2: 1, in_3: 1, in_4: 1, sel: 3", out, 1)
in_1 = 1'b0;
`assert("mux in_1: 0, in_2: 1, in_3: 1, in_4: 1, sel: 1", out, 1)
in_2 = 1'b0;
`assert("mux in_1: 0, in_2: 0, in_3: 1, in_4: 1, sel: 1", out, 1)
sel = 2'b00;
`assert("mux in_1: 0, in_2: 0, in_3: 1, in_4: 1, sel: 0", out, 0)
`end_message
end
endmodule : tb_mux4_1

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tb/tb_registers_bank.v Normal file
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`timescale 1ns / 1ps
`include "tb_tools.vh"
module tb_registers_bank ();
reg clk;
reg reset;
integer i;
reg we;
reg [4:0] sel_in;
reg [4:0] sel_out_a;
reg [4:0] sel_out_b;
reg [31:0] data_in;
wire [31:0] data_out_a;
wire [31:0] data_out_b;
registers_bank registers_bank (
.clock(clk),
.reset(reset),
.we(we),
.sel_in(sel_in),
.sel_out_a(sel_out_a),
.sel_out_b(sel_out_b),
.data_in(data_in),
.data_out_a(data_out_a),
.data_out_b(data_out_b)
);
initial begin
reset = 1'b1;
#10
reset = 1'b0;
end
initial begin
clk = 1'b0;
for (i = 0; i < 100; i = i + 1) begin
#1 clk = ~clk;
end
end
initial begin
we = 1'b0;
sel_in = 5'b00000;
sel_out_a = 5'b00000;
sel_out_b = 5'b00000;
data_in = 32'b0;
`assert("registers_bank we: 0, sel_in: 0, sel_out_a: 0, sel_out_b: 0, data_in: 0", data_out_a, 0)
we = 1'b1;
data_in = 32'b1;
`assert("registers_bank we: 1, sel_in: 0, sel_out_a: 0, sel_out_b: 0, data_in: 1", data_out_a, 0)
sel_in = 5'b00001;
`assert("registers_bank we: 1, sel_in: 1, sel_out_a: 0, sel_out_b: 0, data_in: 1", data_out_a, 0)
sel_out_a = 5'b00001;
`assert("registers_bank we: 1, sel_in: 1, sel_out_a: 1, sel_out_b: 0, data_in: 1", data_out_a, 1)
`assert("registers_bank we: 1, sel_in: 1, sel_out_a: 1, sel_out_b: 0, data_in: 1", data_out_b, 0)
sel_out_b = 5'b00001;
`assert("registers_bank we: 1, sel_in: 1, sel_out_a: 1, sel_out_b: 1, data_in: 1", data_out_b, 1)
we = 1'b0;
data_in = 32'b11;
`assert("registers_bank we: 0, sel_in: 1, sel_out_a: 1, sel_out_b: 1, data_in: 3", data_out_a, 1)
`assert("registers_bank we: 0, sel_in: 1, sel_out_a: 1, sel_out_b: 1, data_in: 3", data_out_b, 1)
data_in = 32'b111;
sel_in = 5'b11111;
sel_out_a = 5'b11111;
we = 1'b1;
`assert("registers_bank we: 1, sel_in: 31, sel_out_a: 31, sel_out_b: 1, data_in: 7", data_out_a, 7)
`assert("registers_bank we: 1, sel_in: 31, sel_out_a: 31, sel_out_b: 1, data_in: 7", data_out_b, 1)
`end_message
end
endmodule : tb_registers_bank

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`define assert(message, expected, got) \ `define assert(message, expected, got) \
#20 \ #4 \
if(expected !== got) begin \ if(expected !== got) begin \
$display("\033[0;31m[FAILED]\033[0m : %s - got: %d, expected: %d", message, expected, got); \ $display("\033[0;31m[FAILED]\033[0m : %s - got: %d, expected: %d", message, expected, got); \
end end