brice/RISC-V_Verilog
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brice.boisson 7c1a871e99 Add: tb registers bank
2023-10-24 20:08:36 +09:00
rtl
Fix: change alu op_code to func
2023-10-24 19:39:42 +09:00
scripts
Add: basic element for risc-v single cycle cpu
2023-10-20 18:48:18 +09:00
sim
Add: Makefile
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tb
Add: tb registers bank
2023-10-24 20:08:36 +09:00
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Makefile
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README.md
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README.md

This project is an educative project with the goal to implement a basic RISC-V CPU in Verilog for an educative purpose.

Description
No description provided
Readme 127 KiB
Languages
Verilog 75.1%
Assembly 10.9%
Shell 5.6%
SystemVerilog 5.1%
Python 2.9%
Other 0.4%