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RISC-V_Verilog
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Add: Formating test output

This commit is contained in:
brice.boisson 2023-11-24 19:28:08 +09:00
parent 82474c8d16
commit 81268259ff
2 changed files with 52 additions and 12 deletions
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52
scripts/run_test.sh
View File

@ -1,6 +1,6 @@
#!/bin/sh
rm -rf runtime_test.tmp final_test.tmp
rm -rf work runtime_test.tmp final_test.tmp
SCRIPT_FOLDER="./../scripts"
TEST_BENCH_FOLDER="./../tb"
@ -17,7 +17,7 @@ fi
run_test ()
{
TEST_FILE_PATH=$1
if [ ! -f $TEST_FILE_PATH ]; then
if [ ! -f "$TEST_FILE_PATH" ]; then
echo "test file: ""$TEST_FILE_PATH"": does not exit"
exit 1
fi
@ -26,20 +26,58 @@ run_test ()
python3 ./${SCRIPT_FOLDER}/gen_test.py $TEST_FILE_PATH
if [ -z $2 ]; then
vsim -c -do "do simu.do; quit -f"
# display only if line contains '[FAIL]' or '[PASS]'
vsim -c -do "do simu.do; quit -f" >& /dev/null # | tr -cd '[:print:]\t\n' | print_result # print_result #| sed -n 's/^# \(.*\[FAIL\|\PASS\].*\)/\1/p'
else
vsim -do "do simu.do"
fi
print_result $(basename $TEST_FILE_PATH .S)
}
print_result ()
{
while read line; do
if [[ $line = *"# Errors: "* ]]; then
# Errors: 0, Warnings: 0 - get only the number of errors
if [ $(echo "$line" | sed 's/^# Errors: \([[:digit:]]*\).*/\1/') -ne 0 ]; then
cat ./transcript
return 1
fi
fi
done < ./transcript
nb_test=0
nb_pass=0
nb_fail=0
while read line; do
if [[ $line = *"[FAIL]"* ]]; then
echo "$line" | cut -c 3-
((nb_fail++))
((nb_test++))
elif [[ $line == *"[PASS]"* ]]; then
((nb_pass++))
((nb_test++))
elif [[ $line == *"\*\* Warning"* ]]; then
echo "$line" | cut -c 3-
fi
done < ./transcript
bold=$(tput bold)
normal=$(tput sgr0)
echo -e "[\033[0;34m$bold$1$normal\033[0m]$bold Test: $nb_test | Passed: $normal\033[0;32m$bold$nb_pass$normal\033[0m$bold | Failed: $normal\033[0;31m$bold$nb_fail$normal\033[0m"
}
if [ -z "$TEST_FILE" ] || [ "$TEST_FILE" = "all" ]; then
./${SCRIPT_FOLDER}/gen_simu_do.sh "$TEST_BENCH"
if [ -z $2 ]; then
vsim -c -do "do simu.do; quit -f"
vsim -c -do "do simu.do; quit -f" >& /dev/null
else
vsim -do "do simu.do"
fi
print_result $TEST_BENCH
fi
if [ ! -z "$TEST_FILE" ]; then
@ -51,11 +89,11 @@ if [ ! -z "$TEST_FILE" ]; then
./${SCRIPT_FOLDER}/gen_simu_do.sh "$TEST_BENCH""-dyn"
if [ "$TEST_FILE" == "all" ]; then
for f in "$TEST_BENCH_FOLDER""/""$TEST_FOLDER""/*"; do
run_test $f $2
for f in "$TEST_BENCH_FOLDER""/""$TEST_FOLDER"/*; do
run_test "$f" "$2"
done
else
run_test $TEST_FILE".S" $2
run_test "$TEST_BENCH_FOLDER""/""$TEST_FOLDER""/"$TEST_FILE".S" "$2"
fi
fi

12
tb/tb_tools.vh
View File

@ -1,15 +1,17 @@
`define assert(message, expected, got) \
#4 \
if(expected !== got) begin \
$display("\033[0;31m[FAILED]\033[0m : %s - got: %d, expected: %d", message, expected, got); \
end
$display("\033[0;31m[FAIL]\033[0m %s - got: %d, expected: %d", message, expected, got); \
end else \
$display("\033[0;32m[PASS]\033[0m %s", message);
`define assert_no_wait(message, expected, got) \
if(expected !== got) begin \
$display("\033[0;31m[FAILED]\033[0m : %s - got: %d, expected: %d", message, expected, got); \
end
$display("\033[0;31m[FAIL]\033[0m %s - got: %d, expected: %d", message, expected, got); \
end else \
$display("\033[0;32m[PASS]\033[0m %s", message);
`define end_message $display("\033[0;32mIf no \033[0m[FAILED]\033[0;32m messages, all tests passed!\033[0m");
`define end_message $display("\033[0;32mIf no \033[0mFAIL\033[0;32m messages, all tests passed!\033[0m");
`define next_cycle \
#1 clk = ~clk; \