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Add: name of the dynamic test following the tested element

This commit is contained in:
brice.boisson 2023-11-25 19:28:17 +09:00
parent 9ac36fa030
commit 86abae02eb
2 changed files with 34 additions and 14 deletions
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26
tb/tb_risc_v_cpu-dyn.v
View File

@ -22,6 +22,8 @@ module tb_risc_v_cpu ();
integer curent_addr; integer curent_addr;
integer res; integer res;
reg [8:0] dump; reg [8:0] dump;
reg [50*8:1] message;
integer size;
risc_v_cpu risc_v_cpu ( risc_v_cpu risc_v_cpu (
.clock(clk), .clock(clk),
@ -113,29 +115,29 @@ module tb_risc_v_cpu ();
`next_cycle `next_cycle
if (test[curent_addr][5:0] != 6'b111111) begin if (test[curent_addr][5:0] != 6'b111111) begin
if (test[curent_addr][5:0] < 6'b100000) begin if (test[curent_addr][5:0] < 6'b100000) begin
`assert_no_wait("TEST - REG", risc_v_cpu.registers_bank.registers[test[curent_addr][4:0]], test[curent_addr][37:6]) `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][5:0], risc_v_cpu.registers_bank.registers[test[curent_addr][4:0]], test[curent_addr][37:6])
end else if (test[curent_addr][5:0] == 6'b100000) begin end else if (test[curent_addr][5:0] == 6'b100000) begin
`assert_no_wait("TEST - PC", risc_v_cpu.program_counter.pc_addr, test[curent_addr][37:6]) `assert_no_wait_pc("RUNTIME", curent_addr, risc_v_cpu.program_counter.pc_addr, test[curent_addr][37:6])
end else if (test[curent_addr][5:0] > 6'b100000) begin end else if (test[curent_addr][5:0] > 6'b100000) begin
`assert_no_wait("TEST - MEM", risc_v_cpu.memory.memory[test[curent_addr][5:0]], test[curent_addr][37:6]) `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][5:0], risc_v_cpu.memory.memory[test[curent_addr][5:0]], test[curent_addr][37:6])
end end
end end
if (test[curent_addr][43:38] != 6'b111111) begin if (test[curent_addr][43:38] != 6'b111111) begin
if (test[curent_addr][43:38] < 6'b100000) begin if (test[curent_addr][43:38] < 6'b100000) begin
`assert_no_wait("TEST - REG", risc_v_cpu.registers_bank.registers[test[curent_addr][42:38]], test[curent_addr][75:44]) `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][43:38], risc_v_cpu.registers_bank.registers[test[curent_addr][42:38]], test[curent_addr][75:44])
end else if (test[curent_addr][43:38] == 6'b100000) begin end else if (test[curent_addr][43:38] == 6'b100000) begin
`assert_no_wait("TEST - PC", risc_v_cpu.program_counter.pc_addr, test[curent_addr][75:44]) `assert_no_wait_pc("RUNTIME", curent_addr, risc_v_cpu.program_counter.pc_addr, test[curent_addr][75:44])
end else if (test[curent_addr][43:38] > 6'b100000) begin end else if (test[curent_addr][43:38] > 6'b100000) begin
`assert_no_wait("TEST - MEM", risc_v_cpu.memory.memory[test[curent_addr][43:38]], test[curent_addr][75:44]) `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][43:38], risc_v_cpu.memory.memory[test[curent_addr][43:38]], test[curent_addr][75:44])
end end
end end
if (test[curent_addr][81:76] != 6'b111111) begin if (test[curent_addr][81:76] != 6'b111111) begin
if (test[curent_addr][81:76] < 6'b100000) begin if (test[curent_addr][81:76] < 6'b100000) begin
`assert_no_wait("TEST - REG", risc_v_cpu.registers_bank.registers[test[curent_addr][80:76]], test[curent_addr][81:76]) `assert_no_wait_reg("RUNTIME", curent_addr, test[curent_addr][81:76], risc_v_cpu.registers_bank.registers[test[curent_addr][80:76]], test[curent_addr][81:76])
end else if (test[curent_addr][81:76] == 6'b100000) begin end else if (test[curent_addr][81:76] == 6'b100000) begin
`assert_no_wait("TEST - PC", risc_v_cpu.program_counter.pc_addr, test[curent_addr][113:83]) `assert_no_wait_pc("RUNTIME", curent_addr, risc_v_cpu.program_counter.pc_addr, test[curent_addr][113:83])
end else if (test[curent_addr][81:76] > 6'b100000) begin end else if (test[curent_addr][81:76] > 6'b100000) begin
`assert_no_wait("TEST - MEM", risc_v_cpu.memory.memory[test[curent_addr][81:76]], test[curent_addr][81:76]) `assert_no_wait_mem("RUNTIME", curent_addr, test[curent_addr][81:76], risc_v_cpu.memory.memory[test[curent_addr][81:76]], test[curent_addr][81:76])
end end
end end
end end
@ -159,11 +161,11 @@ module tb_risc_v_cpu ();
end end
if (reg_number < 6'b100000) begin if (reg_number < 6'b100000) begin
`assert_no_wait("FINAL TEST - REG", risc_v_cpu.registers_bank.registers[reg_number[4:0]], reg_test_value) `assert_no_wait_reg("FINAL", 1'bx, reg_number, risc_v_cpu.registers_bank.registers[reg_number[4:0]], reg_test_value)
end else if (reg_number == 6'b100000) begin end else if (reg_number == 6'b100000) begin
`assert_no_wait("FINAL TEST- PC", risc_v_cpu.program_counter.pc_addr, reg_test_value) `assert_no_wait_pc("FINAL", 1'bx, risc_v_cpu.program_counter.pc_addr, reg_test_value)
end else if (reg_number > 6'b100000) begin end else if (reg_number > 6'b100000) begin
`assert_no_wait("FINAL TEST - MEM", risc_v_cpu.memory.memory[test[curent_addr][5:0]], reg_test_value) `assert_no_wait_mem("FINAL", 1'bx, reg_number, risc_v_cpu.memory.memory[test[curent_addr][5:0]], reg_test_value)
end end
end end

22
tb/tb_tools.vh
View File

@ -1,16 +1,34 @@
`define assert(message, expected, got) \ `define assert(message, expected, got) \
#4 \ #4 \
if(expected !== got) begin \ if(expected !== got) begin \
$display("\033[0;31m[FAIL]\033[0m %s - got: %d, expected: %d", message, expected, got); \ $display("\033[0;31m[FAIL]\033[0m %s - got: %0d, expected: %0d", message, expected, got); \
end else \ end else \
$display("\033[0;32m[PASS]\033[0m %s", message); $display("\033[0;32m[PASS]\033[0m %s", message);
`define assert_no_wait(message, expected, got) \ `define assert_no_wait(message, expected, got) \
if(expected !== got) begin \ if(expected !== got) begin \
$display("\033[0;31m[FAIL]\033[0m %s - got: %d, expected: %d", message, expected, got); \ $display("\033[0;31m[FAIL]\033[0m %s - got: %0d, expected: %0d", message, expected, got); \
end else \ end else \
$display("\033[0;32m[PASS]\033[0m %s", message); $display("\033[0;32m[PASS]\033[0m %s", message);
`define assert_no_wait_reg(message, instr_addr, reg_addr, expected, got) \
if(expected !== got) begin \
$display("\033[0;31m[FAIL]\033[0m %s - INSTR: %0d - REG[%0d] = %0d, got: %0d", message, instr_addr, reg_addr, expected, got); \
end else \
$display("\033[0;32m[PASS]\033[0m %s - INSTR: %0d - REG[%0d] = %0d", message, instr_addr, reg_addr, expected);
`define assert_no_wait_pc(message, instr_addr, expected, got) \
if(expected !== got) begin \
$display("\033[0;31m[FAIL]\033[0m %s - INSTR: %0d - PC = %0d, got: %0d", message, instr_addr, expected, got); \
end else \
$display("\033[0;32m[PASS]\033[0m %s - INSTR: %0d - PC = %0d", message, instr_addr, expected);
`define assert_no_wait_mem(message, instr_addr, mem_addr, expected, got) \
if(expected !== got) begin \
$display("\033[0;31m[FAIL]\033[0m %s - INSTR: %0d - MEM[%0d] = %0d, got: %0d", message, instr_addr, mem_addr, expected, got); \
end else \
$display("\033[0;32m[PASS]\033[0m %s - INSTR: %0d - MEM[%0d] = %0d", message, instr_addr, mem_addr, expected);
`define end_message $display("\033[0;32mIf no \033[0mFAIL\033[0;32m messages, all tests passed!\033[0m"); `define end_message $display("\033[0;32mIf no \033[0mFAIL\033[0;32m messages, all tests passed!\033[0m");
`define next_cycle \ `define next_cycle \