brice/RISC-V_Verilog
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Add: risc-v test bubble sort

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This commit is contained in:
brice.boisson
2023-10-26 17:43:00 +09:00
parent d51ea5c4c8
commit 9613e2566e
6 changed files with 124 additions and 56 deletions
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16
rtl/decoder.v
View File

@@ -50,12 +50,12 @@ endfunction
function [3:0] branch_func(input [2:0] func);
begin
case (func)
3'b000 : branch_func = 4'b0001;
3'b001 : branch_func = 4'b0001;
3'b010 : branch_func = 4'b0011;
3'b011 : branch_func = 4'b0011;
3'b100 : branch_func = 4'b0011;
3'b101 : branch_func = 4'b0011;
3'b000 : branch_func = SUB;
3'b001 : branch_func = SUB;
3'b100 : branch_func = SLT;
3'b101 : branch_func = SLT;
3'b110 : branch_func = SLTU;
3'b111 : branch_func = SLTU;
default : branch_func = 4'b0000;
endcase
end
@@ -66,10 +66,10 @@ function branch_not(input [2:0] func);
case (func)
3'b000 : branch_not = 1;
3'b001 : branch_not = 0;
3'b010 : branch_not = 0;
3'b011 : branch_not = 1;
3'b100 : branch_not = 0;
3'b101 : branch_not = 1;
3'b110 : branch_not = 0;
3'b111 : branch_not = 1;
default : branch_not = 0;
endcase
end

2
rtl/risc_v_cpu.v
View File

@@ -69,7 +69,7 @@ module risc_v_cpu (input clock, reset,
mux2_1 #(2) mux2_pc_sel_branch (
.in_1(pc_is_branch),
.in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 0 ? 1'b1 : 1'b0))}),
.in_2({1'b0, (alu_not ? (~alu_out != 32'b0 ? 1'b1 : 1'b0) : (alu_out != 32'b0 ? 1'b1 : 1'b0))}),
.sel(pc_is_jmp),
.out(pc_sel_in)
);